soc/intel/cannonlake: Update GPIO definitions for Virtual GPIO
Denote appropriate reserved groups as virtual GPIOs in Cannonlake LP/H SoC. Change-Id: I4da161b91f83749b0ae29b387b5c99c1c3f706d8 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/31552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Rizwan Qureshi
Patrick Georgi
parent
db561e6e39
commit
747154074c
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@ -80,7 +80,7 @@ Method (GADD, 1, NotSerialized)
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Subtract (Arg0, GPP_A0, Local1)
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}
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/* GPIO Community 1 */
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If (LAnd (LGreaterEqual (Arg0, GPP_D0), LLessEqual (Arg0, GPIO_RSVD_52)))
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If (LAnd (LGreaterEqual (Arg0, GPP_D0), LLessEqual (Arg0, vSD3_CD_B)))
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{
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Store (PID_GPIOCOM1, Local0)
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Subtract (Arg0, GPP_D0, Local1)
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@ -92,13 +92,13 @@ Method (GADD, 1, NotSerialized)
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Subtract (Arg0, GPD0, Local1)
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}
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/* GPIO Community 3 */
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If (LAnd (LGreaterEqual (Arg0, HDA_BCLK), LLessEqual (Arg0, GPIO_RSVD_78)))
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If (LAnd (LGreaterEqual (Arg0, HDA_BCLK), LLessEqual (Arg0, GPIO_RSVD_38)))
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{
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Store (PID_GPIOCOM1, Local0)
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Subtract (Arg0, HDA_BCLK, Local1)
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}
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/* GPIO Community 04*/
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If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, GPIO_RSVD_67)))
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If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, GPIO_RSVD_27)))
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{
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Store (PID_GPIOCOM4, Local0)
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Subtract (Arg0, GPP_C0, Local1)
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@ -56,7 +56,7 @@ static const struct pad_group cnl_community1_groups[] = {
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INTEL_GPP_BASE(GPP_D0, GPP_D0, GPIO_RSVD_12, 96), /* GPP_D */
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INTEL_GPP_BASE(GPP_D0, GPP_F0, GPP_F23, 128), /* GPP_F */
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INTEL_GPP_BASE(GPP_D0, GPP_H0, GPP_H23, 160), /* GPP_H */
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INTEL_GPP_BASE(GPP_D0, GPIO_RSVD_13, GPIO_RSVD_52, 192),/* VGPIO */
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INTEL_GPP_BASE(GPP_D0, CNV_BTEN, vSD3_CD_B, 192), /* VGPIO */
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};
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/* This community is not visible to the OS */
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@ -67,14 +67,14 @@ static const struct pad_group cnl_community2_groups[] = {
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/* This community is not visible to the OS */
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static const struct pad_group cnl_community3_groups[] = {
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INTEL_GPP(HDA_BCLK, HDA_BCLK, SSP1_TXD), /* AZA */
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INTEL_GPP(HDA_BCLK, GPIO_RSVD_68, GPIO_RSVD_78), /* CPU */
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INTEL_GPP(HDA_BCLK, GPIO_RSVD_28, GPIO_RSVD_38), /* CPU */
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};
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static const struct pad_group cnl_community4_groups[] = {
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INTEL_GPP_BASE(GPP_C0, GPP_C0, GPP_C23, 256), /* GPP_C */
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INTEL_GPP_BASE(GPP_C0, GPP_E0, GPP_E23, 288), /* GPP_E */
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INTEL_GPP(GPP_C0, GPIO_RSVD_53, GPIO_RSVD_61), /* JTAG */
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INTEL_GPP(GPP_C0, GPIO_RSVD_62, GPIO_RSVD_67), /* HVMOS */
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INTEL_GPP(GPP_C0, GPIO_RSVD_13, GPIO_RSVD_21), /* JTAG */
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INTEL_GPP(GPP_C0, GPIO_RSVD_22, GPIO_RSVD_27), /* HVMOS */
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};
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static const struct pad_community cnl_communities[] = {
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@ -97,7 +97,7 @@ static const struct pad_community cnl_communities[] = {
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}, { /* GPP D, F, H, VGPIO */
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.port = PID_GPIOCOM1,
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.first_pad = GPP_D0,
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.last_pad = GPIO_RSVD_52,
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.last_pad = vSD3_CD_B,
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.num_gpi_regs = NUM_GPIO_COM1_GPI_REGS,
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.pad_cfg_base = PAD_CFG_BASE,
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.host_own_reg_0 = HOSTSW_OWN_REG_0,
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@ -129,7 +129,7 @@ static const struct pad_community cnl_communities[] = {
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}, { /* AZA, CPU */
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.port = PID_GPIOCOM3,
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.first_pad = HDA_BCLK,
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.last_pad = GPIO_RSVD_78,
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.last_pad = GPIO_RSVD_38,
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.num_gpi_regs = NUM_GPIO_COM3_GPI_REGS,
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.pad_cfg_base = PAD_CFG_BASE,
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.host_own_reg_0 = HOSTSW_OWN_REG_0,
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@ -145,7 +145,7 @@ static const struct pad_community cnl_communities[] = {
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}, { /* GPP C, E, JTAG, HVMOS */
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.port = PID_GPIOCOM4,
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.first_pad = GPP_C0,
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.last_pad = GPIO_RSVD_67,
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.last_pad = GPIO_RSVD_27,
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.num_gpi_regs = NUM_GPIO_COM4_GPI_REGS,
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.pad_cfg_base = PAD_CFG_BASE,
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.host_own_reg_0 = HOSTSW_OWN_REG_0,
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@ -55,8 +55,8 @@ static const struct pad_group cnl_community1_groups[] = {
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INTEL_GPP_BASE(GPP_C0, GPP_D0, GPP_D23, 96), /* GPP_D */
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INTEL_GPP_BASE(GPP_C0, GPP_G0, GPP_G7, 128), /* GPP_G */
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INTEL_GPP(GPP_C0, GPIO_RSVD_3, GPIO_RSVD_10), /* AZA */
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INTEL_GPP_BASE(GPP_C0, GPIO_RSVD_11, GPIO_RSVD_42, 160),/* VGPIO_0 */
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INTEL_GPP(GPP_C0, GPIO_RSVD_43, GPIO_RSVD_50), /* VGPIO_0 */
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INTEL_GPP_BASE(GPP_C0, CNV_BTEN, vISH_UART1_RTS_B, 160),/* VGPIO_0 */
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INTEL_GPP(GPP_C0, vCNV_BT_I2S_BCLK, vSSP2_RXD), /* VGPIO_1 */
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};
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/* This community is not visible to the OS */
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@ -69,14 +69,14 @@ static const struct pad_group cnl_community3_groups[] = {
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INTEL_GPP_BASE(GPP_K0, GPP_H0, GPP_H23, 224), /* GPP_H */
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INTEL_GPP_BASE(GPP_K0, GPP_E0, GPP_E12, 256), /* GPP_E */
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INTEL_GPP_BASE(GPP_K0, GPP_F0, GPP_F23, 288), /* GPP_F */
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INTEL_GPP(GPP_K0, GPIO_RSVD_51, GPIO_RSVD_59), /* SPI */
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INTEL_GPP(GPP_K0, GPIO_RSVD_11, GPIO_RSVD_19), /* SPI */
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};
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static const struct pad_group cnl_community4_groups[] = {
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INTEL_GPP(GPIO_RSVD_60, GPIO_RSVD_60, GPIO_RSVD_70), /* CPU */
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INTEL_GPP(GPIO_RSVD_60, GPIO_RSVD_71, GPIO_RSVD_79), /* JTAG */
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INTEL_GPP_BASE(GPIO_RSVD_60, GPP_I0, GPP_I14, 320), /* GPP_I */
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INTEL_GPP_BASE(GPIO_RSVD_60, GPP_J0, GPP_J11, 352), /* GPP_J */
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INTEL_GPP(GPIO_RSVD_20, GPIO_RSVD_20, GPIO_RSVD_30), /* CPU */
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INTEL_GPP(GPIO_RSVD_20, GPIO_RSVD_31, GPIO_RSVD_39), /* JTAG */
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INTEL_GPP_BASE(GPIO_RSVD_20, GPP_I0, GPP_I14, 320), /* GPP_I */
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INTEL_GPP_BASE(GPIO_RSVD_20, GPP_J0, GPP_J11, 352), /* GPP_J */
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};
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static const struct pad_community cnl_communities[] = {
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@ -99,7 +99,7 @@ static const struct pad_community cnl_communities[] = {
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}, { /* GPP C, D, G */
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.port = PID_GPIOCOM1,
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.first_pad = GPP_C0,
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.last_pad = GPIO_RSVD_50,
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.last_pad = vSSP2_RXD,
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.num_gpi_regs = NUM_GPIO_COM1_GPI_REGS,
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.pad_cfg_base = PAD_CFG_BASE,
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.host_own_reg_0 = HOSTSW_OWN_REG_0,
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@ -131,7 +131,7 @@ static const struct pad_community cnl_communities[] = {
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}, { /* GPP K, H, E, F */
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.port = PID_GPIOCOM3,
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.first_pad = GPP_K0,
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.last_pad = GPIO_RSVD_59,
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.last_pad = GPIO_RSVD_19,
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.num_gpi_regs = NUM_GPIO_COM3_GPI_REGS,
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.pad_cfg_base = PAD_CFG_BASE,
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.host_own_reg_0 = HOSTSW_OWN_REG_0,
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@ -146,7 +146,7 @@ static const struct pad_community cnl_communities[] = {
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.num_groups = ARRAY_SIZE(cnl_community3_groups),
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}, { /* GPP I, J */
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.port = PID_GPIOCOM4,
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.first_pad = GPIO_RSVD_60,
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.first_pad = GPIO_RSVD_20,
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.last_pad = GPP_J11,
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.num_gpi_regs = NUM_GPIO_COM4_GPI_REGS,
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.pad_cfg_base = PAD_CFG_BASE,
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@ -197,48 +197,48 @@
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#define GPP_H22 139
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#define GPP_H23 140
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/* Group VGPIO */
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#define GPIO_RSVD_13 141
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#define GPIO_RSVD_14 142
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#define GPIO_RSVD_15 143
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#define GPIO_RSVD_16 144
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#define GPIO_RSVD_17 145
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#define GPIO_RSVD_18 146
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#define GPIO_RSVD_19 147
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#define GPIO_RSVD_20 148
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#define GPIO_RSVD_21 149
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#define GPIO_RSVD_22 150
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#define GPIO_RSVD_23 151
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#define GPIO_RSVD_24 152
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#define GPIO_RSVD_25 153
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#define GPIO_RSVD_26 154
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#define GPIO_RSVD_27 155
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#define GPIO_RSVD_28 156
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#define GPIO_RSVD_29 157
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#define GPIO_RSVD_30 158
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#define GPIO_RSVD_31 159
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#define GPIO_RSVD_32 160
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#define GPIO_RSVD_33 161
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#define GPIO_RSVD_34 162
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#define GPIO_RSVD_35 163
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#define GPIO_RSVD_36 164
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#define GPIO_RSVD_37 165
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#define GPIO_RSVD_38 166
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#define GPIO_RSVD_39 167
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#define GPIO_RSVD_40 168
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#define GPIO_RSVD_41 169
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#define GPIO_RSVD_42 170
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#define GPIO_RSVD_43 171
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#define GPIO_RSVD_44 172
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#define GPIO_RSVD_45 173
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#define GPIO_RSVD_46 174
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#define GPIO_RSVD_47 175
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#define GPIO_RSVD_48 176
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#define GPIO_RSVD_49 177
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#define GPIO_RSVD_50 178
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#define GPIO_RSVD_51 179
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#define GPIO_RSVD_52 180
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#define CNV_BTEN 141
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#define CNV_GNEN 142
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#define CNV_WFEN 143
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#define CNV_WCEN 144
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#define CNV_BT_HOST_WAKEB 145
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#define CNV_BT_IF_SELECT 146
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#define vCNV_BT_UART_TXD 147
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#define vCNV_BT_UART_RXD 148
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#define vCNV_BT_UART_CTS_B 149
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#define vCNV_BT_UART_RTS_B 150
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#define vCNV_MFUART1_TXD 151
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#define vCNV_MFUART1_RXD 152
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#define vCNV_MFUART1_CTS_B 153
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#define vCNV_MFUART1_RTS_B 154
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#define vCNV_GNSS_UART_TXD 155
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#define vCNV_GNSS_UART_RXD 156
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#define vCNV_GNSS_UART_CTS_B 157
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#define vCNV_GNSS_UART_RTS_B 158
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#define vUART0_TXD 159
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#define vUART0_RXD 160
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#define vUART0_CTS_B 161
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#define vUART0_RTS_B 162
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#define vISH_UART0_TXD 163
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#define vISH_UART0_RXD 164
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#define vISH_UART0_CTS_B 165
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#define vISH_UART0_RTS_B 166
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#define vISH_UART1_TXD 167
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#define vISH_UART1_RXD 168
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#define vISH_UART1_CTS_B 169
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#define vISH_UART1_RTS_B 170
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#define vCNV_BT_I2S_BCLK 171
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#define vCNV_BT_I2S_WS_SYNC 172
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#define vCNV_BT_I2S_SDO 173
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#define vCNV_BT_I2S_SDI 174
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#define vSSP2_SCLK 175
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#define vSSP2_SFRM 176
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#define vSSP2_TXD 177
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#define vSSP2_RXD 178
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#define vCNV_GNSS_HOST_WAKEB 179
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#define vSD3_CD_B 180
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#define NUM_GPIO_COM1_PADS (GPIO_RSVD_52 - GPP_D0 + 1)
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#define NUM_GPIO_COM1_PADS (vSD3_CD_B - GPP_D0 + 1)
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/* Group C */
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#define GPP_C0 181
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@ -291,24 +291,24 @@
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#define GPP_E22 227
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#define GPP_E23 228
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/* Group Jtag */
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#define GPIO_RSVD_53 229
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#define GPIO_RSVD_54 230
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#define GPIO_RSVD_55 231
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#define GPIO_RSVD_56 232
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#define GPIO_RSVD_57 233
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#define GPIO_RSVD_58 234
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#define GPIO_RSVD_59 235
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#define GPIO_RSVD_60 236
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#define GPIO_RSVD_61 237
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#define GPIO_RSVD_13 229
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#define GPIO_RSVD_14 230
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#define GPIO_RSVD_15 231
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#define GPIO_RSVD_16 232
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#define GPIO_RSVD_17 233
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#define GPIO_RSVD_18 234
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#define GPIO_RSVD_19 235
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#define GPIO_RSVD_20 236
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#define GPIO_RSVD_21 237
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/* Group HVMOS */
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#define GPIO_RSVD_62 238
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#define GPIO_RSVD_63 239
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#define GPIO_RSVD_64 240
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#define GPIO_RSVD_65 241
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#define GPIO_RSVD_66 242
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#define GPIO_RSVD_67 243
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#define GPIO_RSVD_22 238
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#define GPIO_RSVD_23 239
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#define GPIO_RSVD_24 240
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#define GPIO_RSVD_25 241
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#define GPIO_RSVD_26 242
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#define GPIO_RSVD_27 243
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#define NUM_GPIO_COM4_PADS (GPIO_RSVD_67 - GPP_C0 + 1)
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#define NUM_GPIO_COM4_PADS (GPIO_RSVD_27 - GPP_C0 + 1)
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/* Group GPD */
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#define GPD0 244
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@ -337,19 +337,19 @@
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#define SSP1_SFRM 262
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#define SSP1_TXD 263
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/* Group CPU */
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#define GPIO_RSVD_68 264
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#define GPIO_RSVD_69 265
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#define GPIO_RSVD_70 266
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#define GPIO_RSVD_71 267
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#define GPIO_RSVD_72 268
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#define GPIO_RSVD_73 269
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#define GPIO_RSVD_74 270
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#define GPIO_RSVD_75 271
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#define GPIO_RSVD_76 272
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#define GPIO_RSVD_77 273
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#define GPIO_RSVD_78 274
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#define GPIO_RSVD_28 264
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#define GPIO_RSVD_29 265
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#define GPIO_RSVD_30 266
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#define GPIO_RSVD_31 267
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#define GPIO_RSVD_32 268
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#define GPIO_RSVD_33 269
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#define GPIO_RSVD_34 270
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#define GPIO_RSVD_35 271
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#define GPIO_RSVD_36 272
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#define GPIO_RSVD_37 273
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#define GPIO_RSVD_38 274
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#define NUM_GPIO_COM3_PADS (GPIO_RSVD_78 - HDA_BCLK + 1)
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#define NUM_GPIO_COM3_PADS (GPIO_RSVD_38 - HDA_BCLK + 1)
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#define TOTAL_PADS 275
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#endif
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@ -171,50 +171,49 @@
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#define GPIO_RSVD_10 114
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/* VGPIO_0 */
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#define GPIO_RSVD_11 115
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#define GPIO_RSVD_12 116
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#define GPIO_RSVD_13 117
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#define GPIO_RSVD_14 118
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#define GPIO_RSVD_15 119
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#define GPIO_RSVD_16 120
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#define GPIO_RSVD_17 121
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#define GPIO_RSVD_18 122
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#define GPIO_RSVD_19 123
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#define GPIO_RSVD_20 124
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#define GPIO_RSVD_21 125
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#define GPIO_RSVD_22 126
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#define GPIO_RSVD_23 127
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#define GPIO_RSVD_24 128
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#define GPIO_RSVD_25 129
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#define GPIO_RSVD_26 130
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#define GPIO_RSVD_27 131
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#define GPIO_RSVD_28 132
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#define GPIO_RSVD_29 133
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#define GPIO_RSVD_30 134
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#define GPIO_RSVD_31 135
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#define GPIO_RSVD_32 136
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#define GPIO_RSVD_33 137
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#define GPIO_RSVD_34 138
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#define GPIO_RSVD_35 139
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#define GPIO_RSVD_36 140
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#define GPIO_RSVD_37 141
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#define GPIO_RSVD_38 142
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#define GPIO_RSVD_39 143
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#define GPIO_RSVD_40 144
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#define GPIO_RSVD_41 145
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#define GPIO_RSVD_42 146
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#define CNV_BTEN 115
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#define CNV_GNEN 116
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#define CNV_WFEN 117
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#define CNV_WCEN 118
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#define CNV_BT_HOST_WAKEB 119
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#define vCNV_GNSS_HOST_WAKEB 120
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#define vSD3_CD_B 121
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#define CNV_BT_IF_SELECT 122
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#define vCNV_BT_UART_TXD 123
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#define vCNV_BT_UART_RXD 124
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#define vCNV_BT_UART_CTS_B 125
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#define vCNV_BT_UART_RTS_B 126
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#define vCNV_MFUART1_TXD 127
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#define vCNV_MFUART1_RXD 128
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#define vCNV_MFUART1_CTS_B 129
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#define vCNV_MFUART1_RTS_B 130
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#define vCNV_GNSS_UART_TXD 131
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#define vCNV_GNSS_UART_RXD 132
|
||||
#define vCNV_GNSS_UART_CTS_B 133
|
||||
#define vCNV_GNSS_UART_RTS_B 134
|
||||
#define vUART0_TXD 135
|
||||
#define vUART0_RXD 136
|
||||
#define vUART0_CTS_B 137
|
||||
#define vUART0_RTSB 138
|
||||
#define vISH_UART0_TXD 139
|
||||
#define vISH_UART0_RXD 140
|
||||
#define vISH_UART0_CTS_B 141
|
||||
#define vISH_UART0_RTSB 142
|
||||
#define vISH_UART1_TXD 143
|
||||
#define vISH_UART1_RXD 144
|
||||
#define vISH_UART1_CTS_B 145
|
||||
#define vISH_UART1_RTS_B 146
|
||||
/* VGPIO_1 */
|
||||
#define GPIO_RSVD_43 147
|
||||
#define GPIO_RSVD_44 148
|
||||
#define GPIO_RSVD_45 149
|
||||
#define GPIO_RSVD_46 150
|
||||
#define GPIO_RSVD_47 151
|
||||
#define GPIO_RSVD_48 152
|
||||
#define GPIO_RSVD_49 153
|
||||
#define GPIO_RSVD_50 154
|
||||
#define vCNV_BT_I2S_BCLK 147
|
||||
#define vCNV_BT_I2S_WS_SYNC 148
|
||||
#define vCNV_BT_I2S_SDO 149
|
||||
#define vCNV_BT_I2S_SDI 150
|
||||
#define vSSP2_SCLK 151
|
||||
#define vSSP2_SFRM 152
|
||||
#define vSSP2_TXD 153
|
||||
#define vSSP2_RXD 154
|
||||
|
||||
#define NUM_GPIO_COM1_PADS (GPIO_RSVD_50 - GPP_C0 + 1)
|
||||
#define NUM_GPIO_COM1_PADS (vSSP2_RXD - GPP_C0 + 1)
|
||||
|
||||
/* Group K */
|
||||
#define GPP_K0 155
|
||||
|
|
@ -310,41 +309,41 @@
|
|||
#define GPP_F23 239
|
||||
|
||||
/* SPI */
|
||||
#define GPIO_RSVD_51 240
|
||||
#define GPIO_RSVD_52 241
|
||||
#define GPIO_RSVD_53 242
|
||||
#define GPIO_RSVD_54 243
|
||||
#define GPIO_RSVD_55 244
|
||||
#define GPIO_RSVD_56 245
|
||||
#define GPIO_RSVD_57 246
|
||||
#define GPIO_RSVD_58 247
|
||||
#define GPIO_RSVD_59 248
|
||||
#define GPIO_RSVD_11 240
|
||||
#define GPIO_RSVD_12 241
|
||||
#define GPIO_RSVD_13 242
|
||||
#define GPIO_RSVD_14 243
|
||||
#define GPIO_RSVD_15 244
|
||||
#define GPIO_RSVD_16 245
|
||||
#define GPIO_RSVD_17 246
|
||||
#define GPIO_RSVD_18 247
|
||||
#define GPIO_RSVD_19 248
|
||||
|
||||
#define NUM_GPIO_COM3_PADS (GPIO_RSVD_59 - GPP_K0 + 1)
|
||||
#define NUM_GPIO_COM3_PADS (GPIO_RSVD_19 - GPP_K0 + 1)
|
||||
|
||||
/* CPU */
|
||||
#define GPIO_RSVD_60 249
|
||||
#define GPIO_RSVD_61 250
|
||||
#define GPIO_RSVD_62 251
|
||||
#define GPIO_RSVD_63 252
|
||||
#define GPIO_RSVD_64 253
|
||||
#define GPIO_RSVD_65 254
|
||||
#define GPIO_RSVD_66 255
|
||||
#define GPIO_RSVD_67 256
|
||||
#define GPIO_RSVD_68 257
|
||||
#define GPIO_RSVD_69 258
|
||||
#define GPIO_RSVD_70 259
|
||||
#define GPIO_RSVD_20 249
|
||||
#define GPIO_RSVD_21 250
|
||||
#define GPIO_RSVD_22 251
|
||||
#define GPIO_RSVD_23 252
|
||||
#define GPIO_RSVD_24 253
|
||||
#define GPIO_RSVD_25 254
|
||||
#define GPIO_RSVD_26 255
|
||||
#define GPIO_RSVD_27 256
|
||||
#define GPIO_RSVD_28 257
|
||||
#define GPIO_RSVD_29 258
|
||||
#define GPIO_RSVD_30 259
|
||||
|
||||
/* JTAG */
|
||||
#define GPIO_RSVD_71 260
|
||||
#define GPIO_RSVD_72 261
|
||||
#define GPIO_RSVD_73 262
|
||||
#define GPIO_RSVD_74 263
|
||||
#define GPIO_RSVD_75 264
|
||||
#define GPIO_RSVD_76 265
|
||||
#define GPIO_RSVD_77 266
|
||||
#define GPIO_RSVD_78 267
|
||||
#define GPIO_RSVD_79 268
|
||||
#define GPIO_RSVD_31 260
|
||||
#define GPIO_RSVD_32 261
|
||||
#define GPIO_RSVD_33 262
|
||||
#define GPIO_RSVD_34 263
|
||||
#define GPIO_RSVD_35 264
|
||||
#define GPIO_RSVD_36 265
|
||||
#define GPIO_RSVD_37 266
|
||||
#define GPIO_RSVD_38 267
|
||||
#define GPIO_RSVD_39 268
|
||||
|
||||
/* Group I */
|
||||
#define GPP_I0 269
|
||||
|
|
@ -362,9 +361,9 @@
|
|||
#define GPP_I12 281
|
||||
#define GPP_I13 282
|
||||
#define GPP_I14 283
|
||||
#define GPIO_RSVD_80 284
|
||||
#define GPIO_RSVD_81 285
|
||||
#define GPIO_RSVD_82 286
|
||||
#define GPIO_RSVD_40 284
|
||||
#define GPIO_RSVD_41 285
|
||||
#define GPIO_RSVD_42 286
|
||||
|
||||
/* Group J */
|
||||
#define GPP_J0 287
|
||||
|
|
|
|||
Loading…
Reference in New Issue