soc/intel/cannonlake: Add northbridge dsdt table
Add ACPI dsdt table for northbridge, report proper resources in dsdt entries. TEST=Boot up into OS fine. Change-Id: I382d87da087ae7828eaa7ff28bc9597a332ca5bc Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Lijian Zhao
Aaron Durbin
parent
c1a4928609
commit
747f05675e
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@ -15,8 +15,327 @@
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* GNU General Public License for more details.
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*/
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#include <soc/iomap.h>
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#define BASE_32GB 0x800000000
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#define SIZE_16GB 0x400000000
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Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID
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Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID
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Name (_SEG, Zero) // _SEG: PCI Segment
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Name (_ADR, Zero) // _ADR: Address
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Name (_UID, Zero) // _UID: Unique ID
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Device (MCHC)
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{
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Name (_ADR, 0x00000000)
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OperationRegion (MCHP, PCI_Config, 0x00, 0x100)
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Field (MCHP, DWordAcc, NoLock, Preserve)
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{
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Offset(0x40), /* EPBAR (0:0:0:40) */
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EPEN, 1, /* Enable */
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, 11,
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EPBR, 20, /* EPBAR [31:12] */
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Offset(0x48), /* MCHBAR (0:0:0:48) */
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MHEN, 1, /* Enable */
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, 14,
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MHBR, 17, /* MCHBAR [31:15] */
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Offset(0x60), /* PCIEXBAR (0:0:0:60) */
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PXEN, 1, /* Enable */
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PXSZ, 2, /* PCI Express Size */
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, 23,
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PXBR, 6, /* PCI Express BAR [31:26] */
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Offset(0x68), /* DMIBAR (0:0:0:68) */
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DIEN, 1, /* Enable */
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, 11,
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DIBR, 20, /* DMIBAR [31:12] */
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Offset (0xa0), /* Top of Used Memory */
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TOM, 64,
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Offset (0xa8), /* Top of Upper Used Memory */
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TUUD, 64,
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Offset (0xbc), /* Top of Low Used Memory */
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TLUD, 32,
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}
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}
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Name (MCRS, ResourceTemplate ()
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{
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/* Bus Numbers */
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WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
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0x0000, 0x0000, 0x00ff, 0x0000, 0x0100)
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/* IO Region 0 */
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DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode,
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EntireRange,
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0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8)
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/* PCI Config Space */
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Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
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/* IO Region 1 */
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DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode,
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EntireRange,
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0x0000, 0x0d00, 0xffff, 0x0000, 0xf300)
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/* VGA memory (0xa0000-0xbffff) */
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
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0x00020000)
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/* OPROM reserved (0xc0000-0xc3fff) */
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
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0x00004000)
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/* OPROM reserved (0xc4000-0xc7fff) */
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
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0x00004000)
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/* OPROM reserved (0xc8000-0xcbfff) */
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
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0x00004000)
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/* OPROM reserved (0xcc000-0xcffff) */
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
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0x00004000)
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/* OPROM reserved (0xd0000-0xd3fff) */
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
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0x00004000)
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/* OPROM reserved (0xd4000-0xd7fff) */
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
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0x00004000)
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/* OPROM reserved (0xd8000-0xdbfff) */
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
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0x00004000)
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/* OPROM reserved (0xdc000-0xdffff) */
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
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0x00004000)
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/* BIOS Extension (0xe0000-0xe3fff) */
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
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0x00004000)
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/* BIOS Extension (0xe4000-0xe7fff) */
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
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0x00004000)
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/* BIOS Extension (0xe8000-0xebfff) */
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
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0x00004000)
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/* BIOS Extension (0xec000-0xeffff) */
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000ec000, 0x000effff, 0x00000000,
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0x00004000)
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/* System BIOS (0xf0000-0xfffff) */
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
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0x00010000)
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/* PCI Memory Region (TLUD - 0xdfffffff) */
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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NonCacheable, ReadWrite,
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0x00000000, 0x00000000, 0xdfffffff, 0x00000000,
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0xE0000000,,, PM01)
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/* PCI Memory Region (TUUD - (TUUD + ABOVE_4G_MMIO_SIZE)) */
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QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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NonCacheable, ReadWrite,
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0x00000000, 0x10000, 0x1ffff, 0x00000000,
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0x10000,,, PM02)
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/* PCH reserved resource (0xfc800000-0xfe7fffff) */
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, PCH_PRESERVED_BASE_ADDRESS, 0xfe7fffff,
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0x00000000, PCH_PRESERVED_BASE_SIZE)
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/* TPM Area (0xfed40000-0xfed47fff) */
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0xfed40000, 0xfed47fff, 0x00000000,
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0x00008000)
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})
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Method (_CRS, 0, Serialized)
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{
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/* Find PCI resource area in MCRS */
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CreateDwordField (^MCRS, ^PM01._MIN, PMIN)
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CreateDwordField (^MCRS, ^PM01._MAX, PMAX)
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CreateDwordField (^MCRS, ^PM01._LEN, PLEN)
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/*
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* Fix up PCI memory region
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* Start with Top of Lower Usable DRAM
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*/
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Store (^MCHC.TLUD, PMIN)
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Add (Subtract (PMAX, PMIN), 1, PLEN)
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/* Patch PM02 range based on Memory Size */
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CreateQwordField (^MCRS, ^PM02._MIN, MMIN)
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CreateQwordField (^MCRS, ^PM02._MAX, MMAX)
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CreateQwordField (^MCRS, ^PM02._LEN, MLEN)
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Store (^MCHC.TUUD, Local0)
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If (LLessEqual (Local0, BASE_32GB)) {
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Store (BASE_32GB, MMIN)
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Store (SIZE_16GB, MLEN)
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} Else {
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Store (0, MMIN)
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Store (0, MLEN)
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}
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Subtract (Add (MMIN, MLEN), 1, MMAX)
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Return (^MCRS)
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}
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Name (EP_B, 0) /* to store EP BAR */
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Name (MH_B, 0) /* to store MCH BAR */
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Name (PC_B, 0) /* to store PCIe BAR */
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Name (PC_L, 0) /* to store PCIe BAR Length */
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Name (DM_B, 0) /* to store DMI BAR */
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/* Get MCH BAR */
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Method (GMHB, 0, Serialized)
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{
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If (LEqual (MH_B, 0)) {
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ShiftLeft (\_SB.PCI0.MCHC.MHBR, 15, MH_B)
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}
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Return (MH_B)
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}
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/* Get EP BAR */
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Method (GEPB, 0, Serialized)
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{
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If (LEqual (EP_B, 0)) {
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ShiftLeft (\_SB.PCI0.MCHC.EPBR, 12, EP_B)
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}
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Return (EP_B)
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}
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/* Get PCIe BAR */
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Method (GPCB, 0, Serialized)
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{
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If (LEqual (PC_B, 0)) {
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ShiftLeft (\_SB.PCI0.MCHC.PXBR, 26, PC_B)
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}
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Return (PC_B)
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}
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/* Get PCIe Length */
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Method (GPCL, 0, Serialized)
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{
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If (LEqual (PC_L, 0)) {
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ShiftRight (0x10000000, \_SB.PCI0.MCHC.PXSZ, PC_L)
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}
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Return (PC_L)
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}
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/* Get DMI BAR */
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Method (GDMB, 0, Serialized)
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{
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If (LEqual (DM_B, 0)) {
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ShiftLeft (\_SB.PCI0.MCHC.DIBR, 12, DM_B)
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}
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Return (DM_B)
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}
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/* PCI Device Resource Consumption */
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Device (PDRC)
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{
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Name (_HID, EISAID ("PNP0C02"))
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Name (_UID, 1)
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Name (BUF0, ResourceTemplate ()
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{
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/* MCH BAR _BAS will be updated in _CRS below according to
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* B0:D0:F0:Reg.48h
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*/
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Memory32Fixed (ReadWrite, 0, 0x08000, MCHB)
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/* DMI BAR _BAS will be updated in _CRS below according to
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* B0:D0:F0:Reg.68h
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*/
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Memory32Fixed (ReadWrite, 0, 0x01000, DMIB)
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/* EP BAR _BAS will be updated in _CRS below according to
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* B0:D0:F0:Reg.40h
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*/
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Memory32Fixed (ReadWrite, 0, 0x01000, EGPB)
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/* PCI Express BAR _BAS and _LEN will be updated in
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* _CRS below according to B0:D0:F0:Reg.60h
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*/
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Memory32Fixed (ReadWrite, 0, 0, PCIX)
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/* VTD engine memory range.
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*/
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Memory32Fixed (ReadOnly, VTD_BASE_ADDRESS, VTD_BASE_SIZE)
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/* FLASH range */
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Memory32Fixed (ReadOnly, 0xFFF00000, 0x1000000, FIOH)
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/* Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF) */
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Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000, LIOH)
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/* HPET address decode range */
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Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400)
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})
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Method (_CRS, 0, Serialized)
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{
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CreateDwordField (BUF0, ^MCHB._BAS, MBR0)
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Store (\_SB.PCI0.GMHB (), MBR0)
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CreateDwordField (BUF0, ^DMIB._BAS, DBR0)
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Store (\_SB.PCI0.GDMB (), DBR0)
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CreateDwordField (BUF0, ^EGPB._BAS, EBR0)
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Store (\_SB.PCI0.GEPB (), EBR0)
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CreateDwordField (BUF0, ^PCIX._BAS, XBR0)
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Store (\_SB.PCI0.GPCB (), XBR0)
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CreateDwordField (BUF0, ^PCIX._LEN, XSZ0)
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Store (\_SB.PCI0.GPCL (), XSZ0)
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Return (BUF0)
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}
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}
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@ -69,6 +69,8 @@
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#define PTT_TXT_BASE_ADDRESS 0xfed30800
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#define PTT_PRESENT 0x00070000
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#define VTD_BASE_ADDRESS 0xFED90000
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#define VTD_BASE_SIZE 0x00004000
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/*
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* I/O port address space
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*/
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