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mainboard: Sanitize some superio include paths to be non-local 

This brings mainboard up to being consistent tree-wide now for
all superio header path inclusions.

Change-Id: I00a806ce209ba363c62e3ddd49db9bf599f32149
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8052
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Edward O'Callaghan 2015-01-04 04:17:35 +11:00
parent cab19911ff
commit 74834e0758
11 changed files with 11 additions and 11 deletions
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2
src/mainboard/intel/cougar_canyon2/romstage.c
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@ -33,7 +33,7 @@
#include <console/console.h>
#include <halt.h>
#include <reset.h>
#include "superio/smsc/sio1007/chip.h"
#include <superio/smsc/sio1007/chip.h>
#include <fsp_util.h>
#include "northbridge/intel/fsp_sandybridge/northbridge.h"
#include "northbridge/intel/fsp_sandybridge/raminit.h"

2
src/mainboard/intel/emeraldlake2/romstage.c
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@ -30,7 +30,7 @@
#include <arch/acpi.h>
#include <cbmem.h>
#include <console/console.h>
#include "superio/smsc/sio1007/chip.h"
#include <superio/smsc/sio1007/chip.h>
#include "northbridge/intel/sandybridge/sandybridge.h"
#include "northbridge/intel/sandybridge/raminit.h"
#include "southbridge/intel/bd82x6x/pch.h"

2
src/mainboard/intel/mtarvon/romstage.c
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@ -29,7 +29,7 @@
#include "southbridge/intel/i3100/early_smbus.c"
#include "southbridge/intel/i3100/early_lpc.c"
#include "northbridge/intel/i3100/raminit.h"
#include "superio/intel/i3100/i3100.h"
#include <superio/intel/i3100/i3100.h>
#include "superio/intel/i3100/early_serial.c"
#include "northbridge/intel/i3100/memory_initialized.c"
#include "cpu/x86/bist.h"

2
src/mainboard/intel/truxton/romstage.c
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@ -30,7 +30,7 @@
#include "southbridge/intel/i3100/early_smbus.c"
#include "southbridge/intel/i3100/early_lpc.c"
#include "northbridge/intel/i3100/raminit_ep80579.h"
#include "superio/intel/i3100/i3100.h"
#include <superio/intel/i3100/i3100.h>
#include "cpu/x86/mtrr/earlymtrr.c"
#include "superio/intel/i3100/early_serial.c"
#include "lib/debug.c" // XXX

2
src/mainboard/lenovo/t60/dock.c
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@ -24,7 +24,7 @@
#include <arch/io.h>
#include <delay.h>
#include "dock.h"
#include "superio/nsc/pc87384/pc87384.h"
#include <superio/nsc/pc87384/pc87384.h>
#include "ec/acpi/ec.h"
#include "ec/lenovo/pmh7/pmh7.h"
#include "southbridge/intel/i82801gx/i82801gx.h"

2
src/mainboard/lenovo/x60/dock.c
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@ -26,7 +26,7 @@
#include <arch/io.h>
#include "dock.h"
#include "southbridge/intel/i82801gx/i82801gx.h"
#include "superio/nsc/pc87392/pc87392.h"
#include <superio/nsc/pc87392/pc87392.h>
static void dlpc_write_register(int reg, int value)
{

2
src/mainboard/samsung/lumpy/romstage.c
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@ -44,7 +44,7 @@
#include "option_table.h"
#include "gpio.h"
#if CONFIG_DRIVERS_UART_8250IO
#include "superio/smsc/lpc47n207/lpc47n207.h"
#include <superio/smsc/lpc47n207/lpc47n207.h>
#include "superio/smsc/lpc47n207/early_serial.c"
#endif
#if CONFIG_CHROMEOS

2
src/mainboard/samsung/stumpy/romstage.c
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@ -44,7 +44,7 @@
#include <halt.h>
#include "gpio.h"
#if CONFIG_DRIVERS_UART_8250IO
#include "superio/smsc/lpc47n207/lpc47n207.h"
#include <superio/smsc/lpc47n207/lpc47n207.h>
#include "superio/smsc/lpc47n207/early_serial.c"
#endif
#if CONFIG_CHROMEOS

2
src/mainboard/supermicro/h8qgi/romstage.c
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@ -31,7 +31,7 @@
#include "northbridge/amd/agesa/family10/reset_test.h"
#include <nb_cimx.h>
#include <sb_cimx.h>
#include "superio/nuvoton/wpcm450/wpcm450.h"
#include <superio/nuvoton/wpcm450/wpcm450.h>
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627dhg/w83627dhg.h>

2
src/mainboard/supermicro/h8scm/romstage.c
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@ -31,7 +31,7 @@
#include "northbridge/amd/agesa/family10/reset_test.h"
#include <nb_cimx.h>
#include <sb_cimx.h>
#include "superio/nuvoton/wpcm450/wpcm450.h"
#include <superio/nuvoton/wpcm450/wpcm450.h>
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627dhg/w83627dhg.h>

2
src/mainboard/supermicro/h8scm_fam10/romstage.c
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@ -46,7 +46,7 @@
#include "southbridge/amd/sb700/sb700.h"
#include "southbridge/amd/sb700/smbus.h"
#include "southbridge/amd/sr5650/sr5650.h"
#include "superio/nuvoton/wpcm450/wpcm450.h"
#include <superio/nuvoton/wpcm450/wpcm450.h>
#include "northbridge/amd/amdfam10/debug.c"
static void activate_spd_rom(const struct mem_controller *ctrl)