src: Drop unused '#include <halt.h>'

Change-Id: Ie7afe77053a21bcf6a1bf314570f897d1791a620
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

src/commonlib/storage/bouncebuf.c

@@ -17,7 +17,6 @@
 
 #include <arch/cache.h>
 #include "bouncebuf.h"
-#include <halt.h>
 #include "storage.h"
 #include <string.h>
 #include <commonlib/stdlib.h>

src/commonlib/storage/sdhci.c

@@ -24,7 +24,6 @@
 #include <commonlib/storage.h>
 #include <delay.h>
 #include <endian.h>
-#include <halt.h>
 #include "sdhci.h"
 #include "sd_mmc.h"
 #include "storage.h"

src/cpu/intel/haswell/romstage.c

@@ -21,7 +21,6 @@
 #include <cpu/x86/bist.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
-#include <halt.h>
 #include <lib.h>
 #include <timestamp.h>
 #include <device/pci_def.h>

src/ec/google/chromeec/ec.c

@@ -23,7 +23,6 @@
 #include <bootstate.h>
 #include <delay.h>
 #include <elog.h>
-#include <halt.h>
 #include <reset.h>
 #include <rtc.h>
 #include <stdlib.h>

src/mainboard/google/butterfly/romstage.c

@@ -25,7 +25,6 @@
 #include <northbridge/intel/sandybridge/raminit_native.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <southbridge/intel/common/gpio.h>
-#include <halt.h>
 #if CONFIG(CHROMEOS)
 #include <vendorcode/google/chromeos/chromeos.h>
 #endif

src/mainboard/google/link/romstage.c

@@ -27,7 +27,6 @@
 #include <northbridge/intel/sandybridge/raminit_native.h>
 #include <southbridge/intel/common/gpio.h>
 #include "ec/google/chromeec/ec.h"
-#include <halt.h>
 #include <cbfs.h>
 
 #include <southbridge/intel/bd82x6x/chip.h>

src/mainboard/google/parrot/romstage.c

@@ -25,7 +25,6 @@
 #include <northbridge/intel/sandybridge/raminit_native.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <southbridge/intel/common/gpio.h>
-#include <halt.h>
 #include "ec/compal/ene932/ec.h"
 
 void pch_enable_lpc(void)

src/mainboard/google/stout/romstage.c

@@ -26,7 +26,6 @@
 #include <northbridge/intel/sandybridge/raminit_native.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <southbridge/intel/common/gpio.h>
-#include <halt.h>
 #include <bootmode.h>
 #include <ec/quanta/it8518/ec.h>
 #include "ec.h"

src/mainboard/intel/emeraldlake2/romstage.c

@@ -26,7 +26,6 @@
 #include <northbridge/intel/sandybridge/raminit_native.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <southbridge/intel/common/gpio.h>
-#include <halt.h>
 
 #define SIO_PORT 0x164e
 

src/mainboard/kontron/ktqm77/romstage.c

@@ -21,7 +21,6 @@
 #include <cpu/x86/lapic.h>
 #include <cpu/x86/msr.h>
 #include <device/pci_def.h>
-#include <halt.h>
 #include <northbridge/intel/sandybridge/raminit_native.h>
 #include <northbridge/intel/sandybridge/raminit.h>
 #include <northbridge/intel/sandybridge/sandybridge.h>

src/mainboard/samsung/lumpy/romstage.c

@@ -28,7 +28,6 @@
 #include <northbridge/intel/sandybridge/raminit_native.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <southbridge/intel/common/gpio.h>
-#include <halt.h>
 #include "option_table.h"
 #if CONFIG(DRIVERS_UART_8250IO)
 #include <superio/smsc/lpc47n207/lpc47n207.h>

src/mainboard/samsung/stumpy/romstage.c

@@ -29,7 +29,6 @@
 #include <northbridge/intel/sandybridge/raminit_native.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <southbridge/intel/common/gpio.h>
-#include <halt.h>
 #if CONFIG(DRIVERS_UART_8250IO)
 #include <superio/smsc/lpc47n207/lpc47n207.h>
 #endif

src/northbridge/amd/agesa/family14/state_machine.c

@@ -22,7 +22,6 @@
 #include <device/device.h>
 #include <device/pci_def.h>
 #include <device/pci_ops.h>
-#include <halt.h>
 #include <smp/node.h>
 #include <northbridge/amd/agesa/state_machine.h>
 #include <northbridge/amd/agesa/agesa_helper.h>

src/northbridge/intel/pineview/early_init.c

@@ -21,7 +21,6 @@
 #include <device/pci_ops.h>
 #include <device/pci_def.h>
 #include <device/pci.h>
-#include <halt.h>
 #include <string.h>
 #include <northbridge/intel/pineview/pineview.h>
 #include <northbridge/intel/pineview/chip.h>

src/northbridge/intel/pineview/raminit.c

@@ -20,7 +20,6 @@
 #include <console/console.h>
 #include <cpu/x86/cache.h>
 #include <delay.h>
-#include <halt.h>
 #include <lib.h>
 #include "pineview.h"
 #include "raminit.h"

src/northbridge/intel/pineview/romstage.c

@@ -23,6 +23,7 @@
 #include <console/console.h>
 #include <device/pci_ops.h>
 #include <cbmem.h>
+#include <halt.h>
 #include <romstage_handoff.h>
 #include <southbridge/intel/i82801gx/i82801gx.h>
 #include <southbridge/intel/common/gpio.h>

src/northbridge/intel/sandybridge/romstage.c

@@ -27,7 +27,6 @@
 #include <cpu/intel/romstage.h>
 #include <device/pci_def.h>
 #include <device/device.h>
-#include <halt.h>
 #include <northbridge/intel/sandybridge/chip.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <southbridge/intel/common/gpio.h>

src/northbridge/intel/x4x/early_init.c

@@ -26,7 +26,6 @@
 #include <pc80/mc146818rtc.h>
 #include "x4x.h"
 #include <console/console.h>
-#include <halt.h>
 #include <romstage_handoff.h>
 
 void x4x_early_init(void)

src/soc/intel/baytrail/romstage/raminit.c

@@ -22,7 +22,6 @@
 #include <console/console.h>
 #include <device/pci_def.h>
 #include <device/pci_ops.h>
-#include <halt.h>
 #include <mrc_cache.h>
 #include <soc/gpio.h>
 #include <soc/iomap.h>

src/soc/intel/cannonlake/pmutil.c

@@ -30,7 +30,6 @@
 #include <intelblocks/pmclib.h>
 #include <intelblocks/rtc.h>
 #include <intelblocks/tco.h>
-#include <halt.h>
 #include <stdlib.h>
 #include <soc/gpe.h>
 #include <soc/gpio.h>

src/soc/intel/fsp_broadwell_de/smihandler.c

@@ -23,13 +23,11 @@
 #include <cpu/x86/smm.h>
 #include <spi-generic.h>
 #include <elog.h>
-#include <halt.h>
 #include <soc/lpc.h>
 #include <soc/iomap.h>
 #include <soc/pci_devs.h>
 #include <soc/smm.h>
 
-
 /**
  * @brief Set the EOS bit
  */

src/soc/intel/icelake/pmutil.c

@@ -29,7 +29,6 @@
 #include <intelblocks/pmclib.h>
 #include <intelblocks/rtc.h>
 #include <intelblocks/tco.h>
-#include <halt.h>
 #include <stdlib.h>
 #include <soc/gpe.h>
 #include <soc/gpio.h>

src/soc/intel/skylake/pmutil.c

@@ -27,7 +27,6 @@
 #include <device/pci_def.h>
 #include <console/console.h>
 #include <intelblocks/pmclib.h>
-#include <halt.h>
 #include <intelblocks/lpc_lib.h>
 #include <intelblocks/tco.h>
 #include <stdlib.h>

src/soc/mediatek/mt8183/include/soc/rtc.h

@@ -17,7 +17,6 @@
 #define SOC_MEDIATEK_MT8183_RTC_H
 
 #include <soc/rtc_common.h>
-#include <halt.h>
 
 /* RTC registers */
 enum {

src/soc/mediatek/mt8183/rtc.c

@@ -13,6 +13,7 @@
  * GNU General Public License for more details.
  */
 
+#include <halt.h>
 #include <soc/rtc_common.h>
 #include <soc/rtc.h>
 #include <soc/mt6358.h>

src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c

@@ -14,6 +14,7 @@
  * GNU General Public License for more details.
  */
 
+#include <halt.h>
 #include <stdint.h>
 
 /* Function unit addresses. */

src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c

@@ -14,6 +14,7 @@
  * GNU General Public License for more details.
  */
 
+#include <halt.h>
 #include <stdint.h>
 
 /* Function unit addresses. */

src/southbridge/intel/bd82x6x/smihandler.c

@@ -22,11 +22,6 @@
 #include <device/pci_def.h>
 #include <cpu/x86/smm.h>
 #include <elog.h>
-#include <halt.h>
-#include "pch.h"
-
-#include "nvs.h"
-
 #include <northbridge/intel/sandybridge/sandybridge.h>
 #include <southbridge/intel/bd82x6x/me.h>
 #include <southbridge/intel/common/gpio.h>
@@ -34,6 +29,9 @@
 #include <southbridge/intel/common/pmutil.h>
 #include <southbridge/intel/common/finalize.h>
 
+#include "pch.h"
+#include "nvs.h"
+
 static global_nvs_t *gnvs;
 global_nvs_t *smm_get_gnvs(void)
 {

src/southbridge/intel/i82801gx/smihandler.c

@@ -19,7 +19,6 @@
 #include <cpu/x86/cache.h>
 #include <cpu/x86/smm.h>
 #include <device/pci_def.h>
-#include <halt.h>
 #include <pc80/mc146818rtc.h>
 #include <southbridge/intel/common/pmutil.h>
 #include "i82801gx.h"