From 74b964ec4ace463d0b221a369a754bc86776e594 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Fri, 4 Sep 2015 10:41:02 -0700 Subject: [PATCH] kunimitsu: Clean up mainboard code to match glados Clean up the intel/kunimitsu mainboard code to match the code and cleanups in glados. Many of these are trivial changes that do not impact things in a meaningful way but will make it easier to diff the code and keep the mainboards in sync. - use relative path for mainboard includes to make porting easier - fix trivial style issues to match glados so diffs are clean - pull GPIO configuration into gpio.h and use from there - remove thermal.h as it is not used on this board - make info message BIOS_INFO instead of BIOS_ERR - add support for SPD manufacturer and part number in SMBIOS BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-kunimitsu coreboot Change-Id: I64a053bcec0e0ff25a57f65659f391ab64d9a11a Signed-off-by: Patrick Georgi Original-Commit-Id: e47f0fd3e00a665f07098c7ea0018d51b105d1be Original-Change-Id: Ib787f3ccc63115de48c4d608ca2bd81b58d24b6c Original-Signed-off-by: Duncan Laurie Original-Reviewed-on: https://chromium-review.googlesource.com/297752 Original-Reviewed-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/11576 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/mainboard/intel/kunimitsu/acpi/dptf.asl | 4 - .../intel/kunimitsu/acpi/mainboard.asl | 173 +++++++++--------- .../intel/kunimitsu/acpi/superio.asl | 2 +- src/mainboard/intel/kunimitsu/acpi_tables.c | 22 --- src/mainboard/intel/kunimitsu/chromeos.c | 4 +- src/mainboard/intel/kunimitsu/devicetree.cb | 3 + src/mainboard/intel/kunimitsu/dsdt.asl | 3 +- src/mainboard/intel/kunimitsu/ec.c | 13 +- src/mainboard/intel/kunimitsu/fadt.c | 3 +- src/mainboard/intel/kunimitsu/gpio.h | 13 ++ src/mainboard/intel/kunimitsu/pei_data.c | 26 ++- src/mainboard/intel/kunimitsu/ramstage.c | 4 + src/mainboard/intel/kunimitsu/romstage.c | 32 ++-- src/mainboard/intel/kunimitsu/spd/spd.c | 23 +-- src/mainboard/intel/kunimitsu/spd/spd.h | 8 +- src/mainboard/intel/kunimitsu/thermal.h | 36 ---- 16 files changed, 167 insertions(+), 202 deletions(-) delete mode 100644 src/mainboard/intel/kunimitsu/thermal.h diff --git a/src/mainboard/intel/kunimitsu/acpi/dptf.asl b/src/mainboard/intel/kunimitsu/acpi/dptf.asl index a056bf534f..742ba7186f 100644 --- a/src/mainboard/intel/kunimitsu/acpi/dptf.asl +++ b/src/mainboard/intel/kunimitsu/acpi/dptf.asl @@ -18,7 +18,6 @@ * Foundation, Inc. */ -/* CPU */ #define DPTF_CPU_PASSIVE 80 #define DPTF_CPU_CRITICAL 90 #define DPTF_CPU_ACTIVE_AC0 90 @@ -53,9 +52,6 @@ Name (CHPS, Package () { Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */ }) -/* Mainboard specific _PDL is 1GHz */ -Name (MPDL, 8) - Name (DTRT, Package () { /* CPU Throttle Effect on CPU */ Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 }, diff --git a/src/mainboard/intel/kunimitsu/acpi/mainboard.asl b/src/mainboard/intel/kunimitsu/acpi/mainboard.asl index 4492a19335..dce1371a4d 100644 --- a/src/mainboard/intel/kunimitsu/acpi/mainboard.asl +++ b/src/mainboard/intel/kunimitsu/acpi/mainboard.asl @@ -20,20 +20,22 @@ #include "../gpio.h" -#define BOARD_TRACKPAD_IRQ 0x33 -#define BOARD_TOUCHSCREEN_IRQ 0x1f +#define BOARD_TOUCHPAD_I2C_ADDR 0x15 +#define BOARD_TOUCHPAD_IRQ TOUCHPAD_INT_L -#define BOARD_TRACKPAD_I2C_ADDR 0x15 -#define BOARD_TOUCHSCREEN_I2C_ADDR 0x10 -#define BOARD_LEFT_SSM4567_I2C_ADDR 0x34 -#define BOARD_RIGHT_SSM4567_I2C_ADDR 0x35 -#define BOARD_AUDIO_CODEC_I2C_ADDR 0x1A +#define BOARD_TOUCHSCREEN_I2C_ADDR 0x10 +#define BOARD_TOUCHSCREEN_IRQ TOUCHSCREEN_INT_L + +#define BOARD_HP_MIC_CODEC_I2C_ADDR 0x1a +#define BOARD_HP_MIC_CODEC_IRQ MIC_INT_L +#define BOARD_LEFT_SPEAKER_AMP_I2C_ADDR 0x34 +#define BOARD_RIGHT_SPEAKER_AMP_I2C_ADDR 0x35 Scope (\_SB) { Device (LID0) { - Name (_HID, EisaId("PNP0C0D")) + Name (_HID, EisaId ("PNP0C0D")) Method (_LID, 0) { Return (\_SB.PCI0.LPCB.EC0.LIDS) @@ -44,9 +46,10 @@ Scope (\_SB) Device (PWRB) { - Name (_HID, EisaId("PNP0C0C")) + Name (_HID, EisaId ("PNP0C0C")) } } + /* * LPC Trusted Platform Module */ @@ -57,13 +60,15 @@ Scope (\_SB.PCI0.LPCB) Scope (\_SB.PCI0.I2C0) { - Device (ETSA) + /* Touchscreen */ + Device (ELTS) { Name (_HID, "ELAN0001") - Name (_DDN, "ELAN Touchscreen") - Name (_UID, 5) - Name (ISTP, 0) /* TouchScreen */ - Name (_CRS, ResourceTemplate() + Name (_DDN, "Elan Touchscreen") + Name (_UID, 1) + Name (_S0W, 4) + + Name (_CRS, ResourceTemplate () { I2cSerialBus ( BOARD_TOUCHSCREEN_I2C_ADDR, @@ -72,11 +77,13 @@ Scope (\_SB.PCI0.I2C0) AddressingMode7Bit, "\\_SB.PCI0.I2C0", ) - Interrupt (ResourceConsumer, Edge, ActiveLow) { + Interrupt (ResourceConsumer, Edge, ActiveLow) + { BOARD_TOUCHSCREEN_IRQ } }) - Method (_STA, 0, NotSerialized) + + Method (_STA) { Return (0xF) } @@ -85,18 +92,18 @@ Scope (\_SB.PCI0.I2C0) Scope (\_SB.PCI0.I2C1) { - Device (ELAN) + /* Touchpad */ + Device (ELTP) { Name (_HID, "ELAN0000") Name (_DDN, "Elan Touchpad") - Name (_UID, 3) - /* Allow device to power off in S0 */ + Name (_UID, 1) Name (_S0W, 4) - Name (ISTP, 1) /* TouchPad */ - Name (_CRS, ResourceTemplate() + + Name (_CRS, ResourceTemplate () { I2cSerialBus ( - BOARD_TRACKPAD_I2C_ADDR, + BOARD_TOUCHPAD_I2C_ADDR, ControllerInitiated, 400000, AddressingMode7Bit, @@ -104,9 +111,10 @@ Scope (\_SB.PCI0.I2C1) ) Interrupt (ResourceConsumer, Edge, ActiveLow) { - BOARD_TRACKPAD_IRQ + BOARD_TOUCHPAD_IRQ } }) + Method (_STA) { Return (0xF) @@ -116,68 +124,45 @@ Scope (\_SB.PCI0.I2C1) Scope (\_SB.PCI0.I2C4) { - // LEFT SSM4567 I2c ADDR 0x34 - Device (LSPK) - { - Name (_HID, "INT343B") - Name (_CID, "INT343B") - Name (_DDN, "Intel(R) Smart Sound Technology Audio Codec") - Name (_UID, 1) - - Name (_CRS, ResourceTemplate() - { - I2cSerialBus ( - BOARD_LEFT_SSM4567_I2C_ADDR, - ControllerInitiated, - 400000, - AddressingMode7Bit, - "\\_SB.PCI0.I2C4", - ) - }) - - Method (_STA, 0, NotSerialized) - { - Return (0xF) // I2S Codec ADI LEFT SSM4567 Enabled - } - } // Device (LSPK) - - // RIGHT SSM4567 I2C ADDR 0x35 - Device (RSPK) - { - Name (_HID, "INT343B") - Name (_CID, "INT343B") - Name (_DDN, "Intel(R) Smart Sound Technology Audio Codec") - Name (_UID, 2) - - Name (_CRS, ResourceTemplate() - { - I2cSerialBus ( - BOARD_RIGHT_SSM4567_I2C_ADDR, - ControllerInitiated, - 400000, - AddressingMode7Bit, - "\\_SB.PCI0.I2C4", - ) - }) - - Method (_STA, 0, NotSerialized) - { - Return (0xF) // I2S Codec ADI RIGHT SSM4567 Enabled - } - } // Device (RSPK) - - // Nuvoton NAU88L25 (I2SC = 2) - Device (HDAC) + /* Headphone Codec */ + Device (HPMC) { Name (_HID, "10508825") - Name (_CID, "10508825") - Name (_DDN, "Intel(R) Smart Sound Technology Audio Codec") + Name (_DDN, "NAU88L25 Codec") Name (_UID, 1) Name (_CRS, ResourceTemplate() { I2cSerialBus ( - BOARD_AUDIO_CODEC_I2C_ADDR, + BOARD_HP_MIC_CODEC_I2C_ADDR, + ControllerInitiated, + 400000, + AddressingMode7Bit, + "\\_SB.PCI0.I2C4", + ) + Interrupt (ResourceConsumer, Edge, ActiveLow) + { + BOARD_HP_MIC_CODEC_IRQ + } + }) + + Method (_STA) + { + Return (0xF) + } + } + + /* Left Speaker Amp */ + Device (SPKL) + { + Name (_HID, "INT343B") + Name (_DDN, "SSM4567 Speaker Amp") + Name (_UID, 0) + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + BOARD_LEFT_SPEAKER_AMP_I2C_ADDR, ControllerInitiated, 400000, AddressingMode7Bit, @@ -185,11 +170,33 @@ Scope (\_SB.PCI0.I2C4) ) }) - Method (_STA, 0, NotSerialized) + Method (_STA) { - Return (0xF) // I2S Codec Enabled + Return (0xF) } - } // Device (HDAC) + } + + /* Right Speaker Amp */ + Device (SPKR) + { + Name (_HID, "INT343B") + Name (_DDN, "SSM4567 Speaker Amp") + Name (_UID, 1) + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + BOARD_RIGHT_SPEAKER_AMP_I2C_ADDR, + ControllerInitiated, + 400000, + AddressingMode7Bit, + "\\_SB.PCI0.I2C4", + ) + }) + + Method (_STA) + { + Return (0xF) + } + } } - - diff --git a/src/mainboard/intel/kunimitsu/acpi/superio.asl b/src/mainboard/intel/kunimitsu/acpi/superio.asl index 747991e7f5..822821e9df 100644 --- a/src/mainboard/intel/kunimitsu/acpi/superio.asl +++ b/src/mainboard/intel/kunimitsu/acpi/superio.asl @@ -18,7 +18,7 @@ */ /* mainboard configuration */ -#include +#include "../ec.h" #define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources #define SIO_EC_HOST_ENABLE // EC Host Interface Resources diff --git a/src/mainboard/intel/kunimitsu/acpi_tables.c b/src/mainboard/intel/kunimitsu/acpi_tables.c index 640cd05d95..801035ef8b 100644 --- a/src/mainboard/intel/kunimitsu/acpi_tables.c +++ b/src/mainboard/intel/kunimitsu/acpi_tables.c @@ -18,36 +18,14 @@ * Foundation, Inc. */ -#include -#include -#include -#include #include #include -#include -#include -#include -#include -#include -#include #include #include -#include "thermal.h" - -extern const unsigned char AmlCode[]; void acpi_create_gnvs(global_nvs_t *gnvs) { acpi_init_gnvs(gnvs); - - /* Disable USB ports in S5 */ - gnvs->s5u0 = 0; - - gnvs->tmps = TEMPERATURE_SENSOR_ID; - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; - gnvs->tmax = MAX_TEMPERATURE; - gnvs->dpte = 1; } unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/intel/kunimitsu/chromeos.c b/src/mainboard/intel/kunimitsu/chromeos.c index 441a5c8391..905de137ac 100644 --- a/src/mainboard/intel/kunimitsu/chromeos.c +++ b/src/mainboard/intel/kunimitsu/chromeos.c @@ -22,11 +22,13 @@ #include #include #include -#include +#include #include #include #include +#include #include + #include "gpio.h" #include "ec.h" diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index f1480f3d7f..3d6908670a 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -16,6 +16,9 @@ chip soc/intel/skylake # EC host command range is in 0x800-0x8ff register "gen1_dec" = "0x00fc0801" + # Enable DPTF + register "dptf_enable" = "1" + # FSP Configuration register "ProbelessTrace" = "0" register "EnableLan" = "0" diff --git a/src/mainboard/intel/kunimitsu/dsdt.asl b/src/mainboard/intel/kunimitsu/dsdt.asl index f9d67af98a..ba1b2637c1 100644 --- a/src/mainboard/intel/kunimitsu/dsdt.asl +++ b/src/mainboard/intel/kunimitsu/dsdt.asl @@ -43,7 +43,8 @@ DefinitionBlock( #include #include } - // Thermal handler + + // Dynamic Platform Thermal Framework #include "acpi/dptf.asl" } diff --git a/src/mainboard/intel/kunimitsu/ec.c b/src/mainboard/intel/kunimitsu/ec.c index c491ad5787..5473cfcf3b 100644 --- a/src/mainboard/intel/kunimitsu/ec.c +++ b/src/mainboard/intel/kunimitsu/ec.c @@ -25,11 +25,9 @@ void mainboard_ec_init(void) { - printk(BIOS_DEBUG, "mainboard_ec_init\n"); - post_code(0xf0); + printk(BIOS_DEBUG, "mainboard: EC init\n"); - /* Restore SCI event mask on resume. */ - if (acpi_slp_type == 3) { + if (acpi_is_wakeup_s3()) { google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | MAINBOARD_EC_S3_WAKE_EVENTS); @@ -39,10 +37,8 @@ void mainboard_ec_init(void) /* Clear pending events */ while (google_chromeec_get_event() != 0) ; - /* - * Set SCI mask.OS may not generate SMI event to set - * this on S3 resume. - */ + + /* Restore SCI event mask */ google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); } else { google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | @@ -51,5 +47,4 @@ void mainboard_ec_init(void) /* Clear wake event mask */ google_chromeec_set_wake_mask(0); - post_code(0xf1); } diff --git a/src/mainboard/intel/kunimitsu/fadt.c b/src/mainboard/intel/kunimitsu/fadt.c index 83a0d366f2..83fe860006 100644 --- a/src/mainboard/intel/kunimitsu/fadt.c +++ b/src/mainboard/intel/kunimitsu/fadt.c @@ -47,6 +47,5 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) acpi_fill_in_fadt(fadt); - header->checksum = - acpi_checksum((void *) fadt, header->length); + header->checksum = acpi_checksum((void *) fadt, header->length); } diff --git a/src/mainboard/intel/kunimitsu/gpio.h b/src/mainboard/intel/kunimitsu/gpio.h index 0ab36f11ce..87380d2fcd 100755 --- a/src/mainboard/intel/kunimitsu/gpio.h +++ b/src/mainboard/intel/kunimitsu/gpio.h @@ -29,8 +29,21 @@ /* BIOS Flash Write Protect */ #define GPIO_PCH_WP GPP_C23 + +/* Memory configuration board straps */ +#define GPIO_MEM_CONFIG_0 GPP_C12 +#define GPIO_MEM_CONFIG_1 GPP_C13 +#define GPIO_MEM_CONFIG_2 GPP_C14 +#define GPIO_MEM_CONFIG_3 GPP_C15 + /* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ #define GPE_EC_WAKE GPE0_LAN_WAK + +/* Input device interrupt configuration */ +#define TOUCHPAD_INT_L GPP_B3_IRQ +#define TOUCHSCREEN_INT_L GPP_E7_IRQ +#define MIC_INT_L GPP_F10_IRQ + /* GPP_E16 is EC_SCI_L. GPP_E group is routed to dword 2 in the GPE0 block. */ #define EC_SCI_GPI GPE0_DW2_16 #define EC_SMI_GPI GPP_E15 diff --git a/src/mainboard/intel/kunimitsu/pei_data.c b/src/mainboard/intel/kunimitsu/pei_data.c index 00451bfa5c..f7525daf2e 100644 --- a/src/mainboard/intel/kunimitsu/pei_data.c +++ b/src/mainboard/intel/kunimitsu/pei_data.c @@ -25,24 +25,22 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { - /* DQ byte map for kunimitsu board */ + /* DQ byte map */ const u8 dq_map[2][12] = { - {0x0F, 0xF0 , 0x00, 0xF0 , 0x0F, 0xF0 , - 0x0F, 0x00 , 0xFF, 0x00 , 0xFF, 0x00}, - {0x0F, 0xF0 , 0x00, 0xF0 , 0x0F, 0xF0 , - 0x0F, 0x00 , 0xFF, 0x00 , 0xFF, 0x00} }; - /* DQS CPU<>DRAM map for kunimitsu board */ + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0 , + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0 , + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; + /* DQS CPU<>DRAM map */ const u8 dqs_map[2][8] = { - {0, 1, 3, 2, 6, 5, 4, 7}, - {2, 3, 0, 1, 6, 7, 4, 5} }; + { 0, 1, 3, 2, 6, 5, 4, 7 }, + { 2, 3, 0, 1, 6, 7, 4, 5 } }; - /* Rcomp resistor*/ - const u16 RcompResistor[3] = {200, 81, 162 }; + /* Rcomp resistor */ + const u16 RcompResistor[3] = { 200, 81, 162 }; - /* Rcomp target*/ - const u16 RcompTarget[5] = {100, 40, 40, 23, 40}; - - pei_data->ec_present = 1; + /* Rcomp target */ + const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; memcpy(pei_data->dq_map, dq_map, sizeof(dq_map)); memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map)); diff --git a/src/mainboard/intel/kunimitsu/ramstage.c b/src/mainboard/intel/kunimitsu/ramstage.c index 563c715a3e..2deaaa303a 100644 --- a/src/mainboard/intel/kunimitsu/ramstage.c +++ b/src/mainboard/intel/kunimitsu/ramstage.c @@ -11,6 +11,10 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. */ #include diff --git a/src/mainboard/intel/kunimitsu/romstage.c b/src/mainboard/intel/kunimitsu/romstage.c index 269f29785b..af16dced97 100644 --- a/src/mainboard/intel/kunimitsu/romstage.c +++ b/src/mainboard/intel/kunimitsu/romstage.c @@ -21,13 +21,12 @@ #include #include +#include #include #include -#include #include #include #include -#include #include #include "gpio.h" #include "spd/spd.h" @@ -45,7 +44,6 @@ void mainboard_romstage_entry(struct romstage_params *params) /* Ensure the EC and PD are in the right mode for recovery */ google_chromeec_early_init(); - post_code(0x31); early_config_gpio(); /* Fill out PEI DATA */ @@ -55,23 +53,14 @@ void mainboard_romstage_entry(struct romstage_params *params) romstage_common(params); } -void mainboard_memory_init_params( - struct romstage_params *params, - MEMORY_INIT_UPD *memory_params) +void mainboard_memory_init_params(struct romstage_params *params, + MEMORY_INIT_UPD *memory_params) { if (params->pei_data->spd_data[0][0][0] != 0) { memory_params->MemorySpdPtr00 = (UINT32)(params->pei_data->spd_data[0][0]); memory_params->MemorySpdPtr10 = (UINT32)(params->pei_data->spd_data[1][0]); - printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_0_0\n", - memory_params->MemorySpdPtr00); - printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_0_1\n", - memory_params->MemorySpdPtr01); - printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_1_0\n", - memory_params->MemorySpdPtr10); - printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_1_1\n", - memory_params->MemorySpdPtr11); } memcpy(memory_params->DqByteMapCh0, params->pei_data->dq_map[0], sizeof(params->pei_data->dq_map[0])); @@ -88,3 +77,18 @@ void mainboard_memory_init_params( memory_params->MemorySpdDataLen = SPD_LEN; memory_params->DqPinsInterleaved = FALSE; } + +void mainboard_add_dimm_info(struct romstage_params *params, + struct memory_info *mem_info, + int channel, int dimm, int index) +{ + /* Set the manufacturer */ + memcpy(&mem_info->dimm[index].mod_id, + ¶ms->pei_data->spd_data[channel][dimm][SPD_MANU_OFF], + sizeof(mem_info->dimm[index].mod_id)); + + /* Set the module part number */ + memcpy(mem_info->dimm[index].module_part_number, + ¶ms->pei_data->spd_data[channel][dimm][SPD_PART_OFF], + sizeof(mem_info->dimm[index].module_part_number)); +} diff --git a/src/mainboard/intel/kunimitsu/spd/spd.c b/src/mainboard/intel/kunimitsu/spd/spd.c index e54f1a6bb1..b8e0be6545 100644 --- a/src/mainboard/intel/kunimitsu/spd/spd.c +++ b/src/mainboard/intel/kunimitsu/spd/spd.c @@ -19,17 +19,18 @@ */ #include +#include #include #include -#include #include #include #include #include -#include -#include -#include -#include +#include + +#include "../boardid.h" +#include "../gpio.h" +#include "spd.h" static void mainboard_print_spd_info(uint8_t spd[]) { @@ -90,10 +91,10 @@ void mainboard_fill_spd_data(struct pei_data *pei_data) int spd_index, sku_id; gpio_t spd_gpios[] = { - GPP_C12, /* PCH_MEM_CONFIG[0] */ - GPP_C13, /* PCH_MEM_CONFIG[1] */ - GPP_C14, /* PCH_MEM_CONFIG[2] */ - GPP_C15, /* PCH_MEM_CONFIG[3] */ + GPIO_MEM_CONFIG_0, + GPIO_MEM_CONFIG_1, + GPIO_MEM_CONFIG_2, + GPIO_MEM_CONFIG_3, }; spd_index = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); @@ -102,8 +103,8 @@ void mainboard_fill_spd_data(struct pei_data *pei_data) * and not SKU ID but on SCRD it indicates SKU. */ sku_id = board_id(); - printk(BIOS_ERR, "SPD index %d\n", spd_index); - printk(BIOS_ERR, "Board ID %d\n", sku_id); + printk(BIOS_INFO, "SPD index %d\n", spd_index); + printk(BIOS_INFO, "Board ID %d\n", sku_id); /* Load SPD data from CBFS */ spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, diff --git a/src/mainboard/intel/kunimitsu/spd/spd.h b/src/mainboard/intel/kunimitsu/spd/spd.h index 18d4e68c00..eaa873b55a 100644 --- a/src/mainboard/intel/kunimitsu/spd/spd.h +++ b/src/mainboard/intel/kunimitsu/spd/spd.h @@ -18,8 +18,8 @@ * Foundation, Inc. */ -#ifndef _MAINBOARD_SPD_H_ -#define _MAINBOARD_SPD_H_ +#ifndef MAINBOARD_SPD_H +#define MAINBOARD_SPD_H #define SPD_LEN 256 @@ -32,6 +32,6 @@ #define SPD_BUS_DEV_WIDTH 8 #define SPD_PART_OFF 128 #define SPD_PART_LEN 18 +#define SPD_MANU_OFF 148 - -#endif /* _MAINBOARD_SPD_H_ */ +#endif diff --git a/src/mainboard/intel/kunimitsu/thermal.h b/src/mainboard/intel/kunimitsu/thermal.h deleted file mode 100644 index 41ce631453..0000000000 --- a/src/mainboard/intel/kunimitsu/thermal.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#ifndef _MAINBOARD_THERMAL_H_ -#define _MAINBOARD_THERMAL_H_ - -#define TEMPERATURE_SENSOR_ID 0 /* PECI */ - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 104 - -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 95 - -/* Tj_max value for calculating PECI CPU temperature */ -/* Tj_max can be read by MSR 0x1A2, BITS[23:16] */ -#define MAX_TEMPERATURE 100 - -#endif /* _MAINBOARD_THERMAL_H_ */