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sb/amd/pi/hudson/smhandler: use common APM_CNT_ACPI_* defines 

The Hudson southbridge code for the AMD binaryPI SoCs had its own ACPI
enable and disable APMC command numbers that didn't match the common
defines in coreboot, so use the common define here to be consistent with
the command numbers in the corresponding FADT fields. Since the only SoC
that still would use this code doesn't select HAVE_SMI_HANDLER, this
won't fix any observable bug, but better fix this before anyone possibly
runs into this.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5e596071e1b5269b616b7a93151648cb86ae77bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
This commit is contained in:
Felix Held 2024-01-08 17:02:23 +01:00
parent 3fc1f0667f
commit 74beb5de84
2 changed files with 2 additions and 4 deletions
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2
src/southbridge/amd/pi/hudson/hudson.h
View File

@ -45,8 +45,6 @@
#define ACPI_SCI_IRQ 9
#define ACPI_SMI_CTL_PORT 0xb2
#define ACPI_SMI_CMD_DISABLE 0xbe
#define ACPI_SMI_CMD_ENABLE 0xef
#define REV_HUDSON_A11 0x11
#define REV_HUDSON_A12 0x12

4
src/southbridge/amd/pi/hudson/smihandler.c
View File

@ -28,12 +28,12 @@ static void hudson_apmc_smi_handler(void)
const uint8_t cmd = inb(ACPI_SMI_CTL_PORT);
switch (cmd) {
case ACPI_SMI_CMD_ENABLE:
case APM_CNT_ACPI_ENABLE:
reg32 = inl(ACPI_PM1_CNT_BLK);
reg32 |= (1 << 0); /* SCI_EN */
outl(reg32, ACPI_PM1_CNT_BLK);
break;
case ACPI_SMI_CMD_DISABLE:
case APM_CNT_ACPI_DISABLE:
reg32 = inl(ACPI_PM1_CNT_BLK);
reg32 &= ~(1 << 0); /* clear SCI_EN */
outl(ACPI_PM1_CNT_BLK, reg32);