lynxpoint: Update device IDs and clock gating setup
- Add device IDs for lynxpoint mobile and LP variants. - Update the clock gating setup based on BWG - Update the SATA programming based on BWG - Add a DEVSLP0 mux config register Change-Id: Icf4d7bab7f3df7adef5eb7c5e310a6995227a0e5 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2649 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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@ -282,7 +282,7 @@ static void azalia_init(struct device *dev)
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pci_write_config32(dev, 0xc4, reg32);
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pci_write_config32(dev, 0xc4, reg32);
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reg8 = pci_read_config8(dev, 0x43);
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reg8 = pci_read_config8(dev, 0x43);
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reg8 |= (1 << 6);
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reg8 |= (1 << 5) | (1 << 6) | (1 << 2) | (1 << 1) | (1 << 0);
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pci_write_config8(dev, 0x43, reg8);
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pci_write_config8(dev, 0x43, reg8);
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/* Additional programming steps */
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/* Additional programming steps */
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@ -69,6 +69,11 @@ struct southbridge_intel_lynxpoint_config {
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uint8_t sata_port_map;
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uint8_t sata_port_map;
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uint32_t sata_port0_gen3_tx;
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uint32_t sata_port0_gen3_tx;
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uint32_t sata_port1_gen3_tx;
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uint32_t sata_port1_gen3_tx;
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/* SATA DEVSLP Mux
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* 0 = port 0 DEVSLP on DEVSLP0/GPIO33
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* 1 = port 3 DEVSLP on DEVSLP0/GPIO33
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*/
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uint8_t sata_devslp_mux;
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uint32_t gen1_dec;
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uint32_t gen1_dec;
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uint32_t gen2_dec;
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uint32_t gen2_dec;
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@ -365,38 +365,67 @@ static void enable_hpet(void)
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static void enable_clock_gating(device_t dev)
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static void enable_clock_gating(device_t dev)
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{
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{
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#if CONFIG_INTEL_LYNXPOINT_LP
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/* LynxPoint LP */
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u32 reg32;
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u32 reg32;
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u16 reg16;
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u16 reg16;
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/* DMI */
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RCBA32_AND_OR(0x2234, ~0UL, 0xf);
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RCBA32_AND_OR(0x2234, ~0UL, 0xf);
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reg16 = pci_read_config16(dev, GEN_PMCON_1);
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reg16 = pci_read_config16(dev, GEN_PMCON_1);
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reg16 |= (1 << 2) | (1 << 11);
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reg16 &= ~((1 << 11) | (1 << 14));
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reg16 |= (1 << 5) | (1 << 6) | (1 << 7) | (1 << 12) | (1 << 13);
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reg16 |= (1 << 2); // PCI CLKRUN# Enable
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pci_write_config16(dev, GEN_PMCON_1, reg16);
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pci_write_config16(dev, GEN_PMCON_1, reg16);
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pch_iobp_update(0xEB007F07, ~0UL, (1 << 31));
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reg32 = pci_read_config32(dev, 0x64);
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pch_iobp_update(0xEB004000, ~0UL, (1 << 7));
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reg32 |= (1 << 6);
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pch_iobp_update(0xEC007F07, ~0UL, (1 << 31));
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pci_write_config32(dev, 0x64, reg32);
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pch_iobp_update(0xEC004000, ~0UL, (1 << 7));
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RCBA32_AND_OR(0x2614, 0x8fffffff, 0x0f006500);
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RCBA32_OR(0x900, 0x0000031f);
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reg32 = RCBA32(CG);
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reg32 = RCBA32(CG);
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reg32 |= (1 << 31);
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reg32 |= (1 << 31); // LPC Dynamic
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reg32 |= (1 << 29) | (1 << 28);
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reg32 |= (1 << 30); // LP LPC
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reg32 |= (1 << 27) | (1 << 26) | (1 << 25) | (1 << 24);
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reg32 |= (1 << 28); // GPIO Dynamic
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reg32 |= (1 << 16);
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reg32 |= (1 << 27); // HPET Dynamic
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reg32 |= (1 << 17);
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reg32 |= (1 << 26); // LP LPC
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reg32 |= (1 << 18);
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reg32 |= (1 << 22); // HDA Dynamic
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reg32 |= (1 << 22);
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reg32 |= (1 << 16); // PCIe Dynamic
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reg32 |= (1 << 23);
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reg32 &= ~(1 << 20);
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reg32 |= (1 << 19);
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reg32 |= (1 << 0);
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reg32 |= (0xf << 1);
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RCBA32(CG) = reg32;
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RCBA32(CG) = reg32;
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RCBA32_OR(0x38c0, 0x7);
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RCBA32_OR(0x3434, 0x7); // LP LPC
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RCBA32_OR(0x36d4, 0x6680c004);
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RCBA32_OR(0x3564, 0x3);
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RCBA32_AND_OR(0x333c, 0xff0fffff, 0x00800000); // SATA
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RCBA32_OR(0x38c0, 0x3c07); // SPI Dynamic
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pch_iobp_update(0xCF000000, ~0UL, 0x00007001);
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pch_iobp_update(0xCE00C000, ~0UL, 0x00000001);
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#else
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/* LynxPoint Mobile */
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u32 reg32;
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u16 reg16;
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/* DMI */
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RCBA32_AND_OR(0x2234, ~0UL, 0xf);
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reg16 = pci_read_config16(dev, GEN_PMCON_1);
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reg16 |= (1 << 11) | (1 << 12) | (1 << 14);
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reg16 |= (1 << 2); // PCI CLKRUN# Enable
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pci_write_config16(dev, GEN_PMCON_1, reg16);
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RCBA32_OR(0x900, (1 << 14));
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reg32 = RCBA32(CG);
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reg32 |= (1 << 22); // HDA Dynamic
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reg32 |= (1 << 31); // LPC Dynamic
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reg32 |= (1 << 16); // PCIe Dynamic
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reg32 |= (1 << 27); // HPET Dynamic
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reg32 |= (1 << 28); // GPIO Dynamic
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RCBA32(CG) = reg32;
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RCBA32_OR(0x38c0, 0x7); // SPI Dynamic
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#endif
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}
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}
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#if CONFIG_HAVE_SMI_HANDLER
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#if CONFIG_HAVE_SMI_HANDLER
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@ -666,6 +695,10 @@ static const unsigned short pci_device_ids[] = {
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0x8c4c, /* Q85 SKU */
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0x8c4c, /* Q85 SKU */
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0x8c4e, /* Q87 SKU */
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0x8c4e, /* Q87 SKU */
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0x8c4f, /* QM87 SKU */
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0x8c4f, /* QM87 SKU */
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0x9c41, /* LP Full Featured Engineering Sample */
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0x9c43, /* LP Premium SKU */
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0x9c45, /* LP Mainstream SKU */
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0x9c47, /* LP Value SKU */
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0 };
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0 };
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static const struct pci_driver pch_lpc __pci_driver = {
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static const struct pci_driver pch_lpc __pci_driver = {
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@ -260,11 +260,13 @@ static struct device_operations device_ops = {
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.ops_pci = &pci_ops,
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.ops_pci = &pci_ops,
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};
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};
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static const unsigned short pci_device_ids[] = { 0x1c10, 0x1c12, 0x1c14, 0x1c16,
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static const unsigned short pci_device_ids[] = {
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0x1c18, 0x1c1a, 0x1c1c, 0x1c1e,
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/* Lynxpoint Mobile */
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0x1e10, 0x1e12, 0x1e14, 0x1e16,
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0x8c10, 0x8c12, 0x8c14, 0x8c16, 0x8c18, 0x8c1a, 0x8c1c, 0x8c1e,
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0x1e18, 0x1e1a, 0x1e1c, 0x1e1e,
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/* Lynxpoint Low Power */
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0 };
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0x9c10, 0x9c12, 0x9c14, 0x9c16, 0x9c18, 0x9c1a,
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0
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};
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static const struct pci_driver pch_pcie __pci_driver = {
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static const struct pci_driver pch_pcie __pci_driver = {
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.ops = &device_ops,
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.ops = &device_ops,
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@ -120,13 +120,37 @@ static void sata_init(struct device *dev)
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/* for AHCI, Port Enable is managed in memory mapped space */
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/* for AHCI, Port Enable is managed in memory mapped space */
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reg16 = pci_read_config16(dev, 0x92);
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reg16 = pci_read_config16(dev, 0x92);
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reg16 &= ~0x3f; /* 6 ports SKU + ORM */
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reg16 &= ~0x3f;
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reg16 |= 0x8000 | config->sata_port_map;
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reg16 |= 0x8000 | config->sata_port_map;
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pci_write_config16(dev, 0x92, reg16);
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pci_write_config16(dev, 0x92, reg16);
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/* Setup register 98h */
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reg32 = pci_read_config16(dev, 0x98);
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reg32 |= 1 << 19; /* BWG step 6 */
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reg32 |= 1 << 22; /* BWG step 5 */
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reg32 &= ~(0x3f << 7);
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reg32 |= 0x04 << 7; /* BWG step 7 */
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reg32 |= 1 << 20; /* BWG step 8 */
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reg32 &= ~(0x03 << 5);
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reg32 |= 1 << 5; /* BWG step 9 */
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reg32 |= 1 << 18; /* BWG step 10 */
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reg32 |= 1 << 29; /* BWG step 11 */
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#if CONFIG_INTEL_LYNXPOINT_LP
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reg32 &= ~((1 << 31) | (1 << 30));
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reg32 |= 1 << 23;
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#endif
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pci_write_config32(dev, 0x98, reg32);
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/* Setup register 9Ch */
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reg16 = 0; /* Disable alternate ID */
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reg16 = 1 << 5; /* BWG step 12 */
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pci_write_config16(dev, 0x9c, reg16);
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/* SATA Initialization register */
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/* SATA Initialization register */
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pci_write_config32(dev, 0x94,
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reg32 = 0x183;
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((config->sata_port_map ^ 0x3f) << 24) | 0x183);
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reg32 |= (config->sata_port_map ^ 0x3f) << 24;
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reg32 |= (config->sata_devslp_mux & 1) << 15;
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pci_write_config32(dev, 0x94, reg32);
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/* Initialize AHCI memory-mapped space */
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/* Initialize AHCI memory-mapped space */
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abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5);
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abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5);
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@ -205,31 +229,29 @@ static void sata_init(struct device *dev)
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config->sata_port1_gen3_tx);
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config->sata_port1_gen3_tx);
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/* Additional Programming Requirements */
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/* Additional Programming Requirements */
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sir_write(dev, 0x04, 0x00001600);
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/* Power Optimizer */
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sir_write(dev, 0x28, 0xa0000033);
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sir_write(dev, 0x64, 0x883c9001);
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reg32 = sir_read(dev, 0x54);
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reg32 &= 0xff000000;
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reg32 |= 0x5555aa;
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sir_write(dev, 0x54, reg32);
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sir_write(dev, 0x64, 0xcccc8484);
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reg32 = sir_read(dev, 0x68);
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reg32 = sir_read(dev, 0x68);
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reg32 &= 0xffff0000;
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reg32 &= 0xffff0000;
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reg32 |= 0xcccc;
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reg32 |= 0x880a;
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sir_write(dev, 0x68, reg32);
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sir_write(dev, 0x68, reg32);
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reg32 = sir_read(dev, 0x78);
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reg32 &= 0x0000ffff;
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reg32 |= 0x88880000;
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sir_write(dev, 0x78, reg32);
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sir_write(dev, 0x84, 0x001c7000);
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sir_write(dev, 0x88, 0x88338822);
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sir_write(dev, 0xa0, 0x001c7000);
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// a4
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sir_write(dev, 0xc4, 0x0c0c0c0c);
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sir_write(dev, 0xc8, 0x0c0c0c0c);
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sir_write(dev, 0xd4, 0x10000000);
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pch_iobp_update(0xea004001, 0x3fffffff, 0xc0000000);
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reg32 = sir_read(dev, 0x60);
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pch_iobp_update(0xea00408a, 0xfffffcff, 0x00000100);
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reg32 |= (1 << 0) | (1 << 1) | (1 << 3);
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sir_write(dev, 0x60, reg32);
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/* Clock Gating */
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sir_write(dev, 0x70, 0x3f00bf1f);
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#if CONFIG_INTEL_LYNXPOINT_LP
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sir_write(dev, 0x54, 0xcf000f0f);
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sir_write(dev, 0x58, 0x00190000);
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#endif
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reg32 = pci_read_config32(dev, 0x300);
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reg32 |= (1 << 17) | (1 << 16);
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reg32 |= (1 << 31) | (1 << 30) | (1 << 29);
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pci_write_config32(dev, 0x300, reg32);
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}
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}
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static void sata_enable(device_t dev)
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static void sata_enable(device_t dev)
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@ -278,9 +300,12 @@ static struct device_operations sata_ops = {
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.ops_pci = &sata_pci_ops,
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.ops_pci = &sata_pci_ops,
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};
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};
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static const unsigned short pci_device_ids[] = { 0x1c00, 0x1c01, 0x1c02, 0x1c03,
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static const unsigned short pci_device_ids[] = {
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0x1e00, 0x1e01, 0x1e02, 0x1e03,
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0x8c00, 0x8c02, 0x8c04, 0x8c06, 0x8c08, 0x8c0e, /* Desktop */
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0 };
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0x8c01, 0x8c03, 0x8c05, 0x8c07, 0x8c09, 0x8c0f, /* Mobile */
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0x9c03, 0x9c05, 0x9c07, 0x9c0f, /* Low Power */
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0
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};
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static const struct pci_driver pch_sata __pci_driver = {
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static const struct pci_driver pch_sata __pci_driver = {
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.ops = &sata_ops,
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.ops = &sata_ops,
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