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lynxpoint: Update device IDs and clock gating setup 

- Add device IDs for lynxpoint mobile and LP variants.
- Update the clock gating setup based on BWG
- Update the SATA programming based on BWG
- Add a DEVSLP0 mux config register

Change-Id: Icf4d7bab7f3df7adef5eb7c5e310a6995227a0e5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2649
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
This commit is contained in:
Duncan Laurie 2012-12-17 11:31:40 -08:00 committed by Stefan Reinauer
parent 045f153a4f
commit 74c0d05cf5
5 changed files with 119 additions and 54 deletions
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2
src/southbridge/intel/lynxpoint/azalia.c
View File

@ -282,7 +282,7 @@ static void azalia_init(struct device *dev)
pci_write_config32(dev, 0xc4, reg32);
reg8 = pci_read_config8(dev, 0x43);
reg8 |= (1 << 6);
reg8 |= (1 << 5) | (1 << 6) | (1 << 2) | (1 << 1) | (1 << 0);
pci_write_config8(dev, 0x43, reg8);
/* Additional programming steps */

5
src/southbridge/intel/lynxpoint/chip.h
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@ -69,6 +69,11 @@ struct southbridge_intel_lynxpoint_config {
uint8_t sata_port_map;
uint32_t sata_port0_gen3_tx;
uint32_t sata_port1_gen3_tx;
/* SATA DEVSLP Mux
* 0 = port 0 DEVSLP on DEVSLP0/GPIO33
* 1 = port 3 DEVSLP on DEVSLP0/GPIO33
*/
uint8_t sata_devslp_mux;
uint32_t gen1_dec;
uint32_t gen2_dec;

75
src/southbridge/intel/lynxpoint/lpc.c
View File

@ -365,38 +365,67 @@ static void enable_hpet(void)
static void enable_clock_gating(device_t dev)
{
#if CONFIG_INTEL_LYNXPOINT_LP
/* LynxPoint LP */
u32 reg32;
u16 reg16;
/* DMI */
RCBA32_AND_OR(0x2234, ~0UL, 0xf);
reg16 = pci_read_config16(dev, GEN_PMCON_1);
reg16 |= (1 << 2) | (1 << 11);
reg16 &= ~((1 << 11) | (1 << 14));
reg16 |= (1 << 5) | (1 << 6) | (1 << 7) | (1 << 12) | (1 << 13);
reg16 |= (1 << 2); // PCI CLKRUN# Enable
pci_write_config16(dev, GEN_PMCON_1, reg16);
pch_iobp_update(0xEB007F07, ~0UL, (1 << 31));
pch_iobp_update(0xEB004000, ~0UL, (1 << 7));
pch_iobp_update(0xEC007F07, ~0UL, (1 << 31));
pch_iobp_update(0xEC004000, ~0UL, (1 << 7));
reg32 = pci_read_config32(dev, 0x64);
reg32 |= (1 << 6);
pci_write_config32(dev, 0x64, reg32);
RCBA32_AND_OR(0x2614, 0x8fffffff, 0x0f006500);
RCBA32_OR(0x900, 0x0000031f);
reg32 = RCBA32(CG);
reg32 |= (1 << 31);
reg32 |= (1 << 29) | (1 << 28);
reg32 |= (1 << 27) | (1 << 26) | (1 << 25) | (1 << 24);
reg32 |= (1 << 16);
reg32 |= (1 << 17);
reg32 |= (1 << 18);
reg32 |= (1 << 22);
reg32 |= (1 << 23);
reg32 &= ~(1 << 20);
reg32 |= (1 << 19);
reg32 |= (1 << 0);
reg32 |= (0xf << 1);
reg32 |= (1 << 31); // LPC Dynamic
reg32 |= (1 << 30); // LP LPC
reg32 |= (1 << 28); // GPIO Dynamic
reg32 |= (1 << 27); // HPET Dynamic
reg32 |= (1 << 26); // LP LPC
reg32 |= (1 << 22); // HDA Dynamic
reg32 |= (1 << 16); // PCIe Dynamic
RCBA32(CG) = reg32;
RCBA32_OR(0x38c0, 0x7);
RCBA32_OR(0x36d4, 0x6680c004);
RCBA32_OR(0x3564, 0x3);
RCBA32_OR(0x3434, 0x7); // LP LPC
RCBA32_AND_OR(0x333c, 0xff0fffff, 0x00800000); // SATA
RCBA32_OR(0x38c0, 0x3c07); // SPI Dynamic
pch_iobp_update(0xCF000000, ~0UL, 0x00007001);
pch_iobp_update(0xCE00C000, ~0UL, 0x00000001);
#else
/* LynxPoint Mobile */
u32 reg32;
u16 reg16;
/* DMI */
RCBA32_AND_OR(0x2234, ~0UL, 0xf);
reg16 = pci_read_config16(dev, GEN_PMCON_1);
reg16 |= (1 << 11) | (1 << 12) | (1 << 14);
reg16 |= (1 << 2); // PCI CLKRUN# Enable
pci_write_config16(dev, GEN_PMCON_1, reg16);
RCBA32_OR(0x900, (1 << 14));
reg32 = RCBA32(CG);
reg32 |= (1 << 22); // HDA Dynamic
reg32 |= (1 << 31); // LPC Dynamic
reg32 |= (1 << 16); // PCIe Dynamic
reg32 |= (1 << 27); // HPET Dynamic
reg32 |= (1 << 28); // GPIO Dynamic
RCBA32(CG) = reg32;
RCBA32_OR(0x38c0, 0x7); // SPI Dynamic
#endif
}
#if CONFIG_HAVE_SMI_HANDLER
@ -666,6 +695,10 @@ static const unsigned short pci_device_ids[] = {
0x8c4c, /* Q85 SKU */
0x8c4e, /* Q87 SKU */
0x8c4f, /* QM87 SKU */
0x9c41, /* LP Full Featured Engineering Sample */
0x9c43, /* LP Premium SKU */
0x9c45, /* LP Mainstream SKU */
0x9c47, /* LP Value SKU */
0 };
static const struct pci_driver pch_lpc __pci_driver = {

12
src/southbridge/intel/lynxpoint/pcie.c
View File

@ -260,11 +260,13 @@ static struct device_operations device_ops = {
.ops_pci = &pci_ops,
};
static const unsigned short pci_device_ids[] = { 0x1c10, 0x1c12, 0x1c14, 0x1c16,
0x1c18, 0x1c1a, 0x1c1c, 0x1c1e,
0x1e10, 0x1e12, 0x1e14, 0x1e16,
0x1e18, 0x1e1a, 0x1e1c, 0x1e1e,
0 };
static const unsigned short pci_device_ids[] = {
/* Lynxpoint Mobile */
0x8c10, 0x8c12, 0x8c14, 0x8c16, 0x8c18, 0x8c1a, 0x8c1c, 0x8c1e,
/* Lynxpoint Low Power */
0x9c10, 0x9c12, 0x9c14, 0x9c16, 0x9c18, 0x9c1a,
0
};
static const struct pci_driver pch_pcie __pci_driver = {
.ops = &device_ops,

79
src/southbridge/intel/lynxpoint/sata.c
View File

@ -120,13 +120,37 @@ static void sata_init(struct device *dev)
/* for AHCI, Port Enable is managed in memory mapped space */
reg16 = pci_read_config16(dev, 0x92);
reg16 &= ~0x3f; /* 6 ports SKU + ORM */
reg16 &= ~0x3f;
reg16 |= 0x8000 | config->sata_port_map;
pci_write_config16(dev, 0x92, reg16);
/* Setup register 98h */
reg32 = pci_read_config16(dev, 0x98);
reg32 |= 1 << 19; /* BWG step 6 */
reg32 |= 1 << 22; /* BWG step 5 */
reg32 &= ~(0x3f << 7);
reg32 |= 0x04 << 7; /* BWG step 7 */
reg32 |= 1 << 20; /* BWG step 8 */
reg32 &= ~(0x03 << 5);
reg32 |= 1 << 5; /* BWG step 9 */
reg32 |= 1 << 18; /* BWG step 10 */
reg32 |= 1 << 29; /* BWG step 11 */
#if CONFIG_INTEL_LYNXPOINT_LP
reg32 &= ~((1 << 31) | (1 << 30));
reg32 |= 1 << 23;
#endif
pci_write_config32(dev, 0x98, reg32);
/* Setup register 9Ch */
reg16 = 0; /* Disable alternate ID */
reg16 = 1 << 5; /* BWG step 12 */
pci_write_config16(dev, 0x9c, reg16);
/* SATA Initialization register */
pci_write_config32(dev, 0x94,
((config->sata_port_map ^ 0x3f) << 24) | 0x183);
reg32 = 0x183;
reg32 |= (config->sata_port_map ^ 0x3f) << 24;
reg32 |= (config->sata_devslp_mux & 1) << 15;
pci_write_config32(dev, 0x94, reg32);
/* Initialize AHCI memory-mapped space */
abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5);
@ -205,31 +229,29 @@ static void sata_init(struct device *dev)
config->sata_port1_gen3_tx);
/* Additional Programming Requirements */
sir_write(dev, 0x04, 0x00001600);
sir_write(dev, 0x28, 0xa0000033);
reg32 = sir_read(dev, 0x54);
reg32 &= 0xff000000;
reg32 |= 0x5555aa;
sir_write(dev, 0x54, reg32);
sir_write(dev, 0x64, 0xcccc8484);
/* Power Optimizer */
sir_write(dev, 0x64, 0x883c9001);
reg32 = sir_read(dev, 0x68);
reg32 &= 0xffff0000;
reg32 |= 0xcccc;
reg32 |= 0x880a;
sir_write(dev, 0x68, reg32);
reg32 = sir_read(dev, 0x78);
reg32 &= 0x0000ffff;
reg32 |= 0x88880000;
sir_write(dev, 0x78, reg32);
sir_write(dev, 0x84, 0x001c7000);
sir_write(dev, 0x88, 0x88338822);
sir_write(dev, 0xa0, 0x001c7000);
// a4
sir_write(dev, 0xc4, 0x0c0c0c0c);
sir_write(dev, 0xc8, 0x0c0c0c0c);
sir_write(dev, 0xd4, 0x10000000);
pch_iobp_update(0xea004001, 0x3fffffff, 0xc0000000);
pch_iobp_update(0xea00408a, 0xfffffcff, 0x00000100);
reg32 = sir_read(dev, 0x60);
reg32 |= (1 << 0) | (1 << 1) | (1 << 3);
sir_write(dev, 0x60, reg32);
/* Clock Gating */
sir_write(dev, 0x70, 0x3f00bf1f);
#if CONFIG_INTEL_LYNXPOINT_LP
sir_write(dev, 0x54, 0xcf000f0f);
sir_write(dev, 0x58, 0x00190000);
#endif
reg32 = pci_read_config32(dev, 0x300);
reg32 |= (1 << 17) | (1 << 16);
reg32 |= (1 << 31) | (1 << 30) | (1 << 29);
pci_write_config32(dev, 0x300, reg32);
}
static void sata_enable(device_t dev)
@ -278,9 +300,12 @@ static struct device_operations sata_ops = {
.ops_pci = &sata_pci_ops,
};
static const unsigned short pci_device_ids[] = { 0x1c00, 0x1c01, 0x1c02, 0x1c03,
0x1e00, 0x1e01, 0x1e02, 0x1e03,
0 };
static const unsigned short pci_device_ids[] = {
0x8c00, 0x8c02, 0x8c04, 0x8c06, 0x8c08, 0x8c0e, /* Desktop */
0x8c01, 0x8c03, 0x8c05, 0x8c07, 0x8c09, 0x8c0f, /* Mobile */
0x9c03, 0x9c05, 0x9c07, 0x9c0f, /* Low Power */
0
};
static const struct pci_driver pch_sata __pci_driver = {
.ops = &sata_ops,