GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mainboard/intel/d510mo: Add Intel D510MO mainboard 

Board uses Pineview native raminit
Board boots from grub to linux kernel

VGA needs work, currently headless machine

Change-Id: I8e459c6d40e0711fac8fb8cfbf31d9cb2aaab3aa
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/10074
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Damien Zammit 2015-05-04 10:41:21 +10:00 committed by Stefan Reinauer
parent 149c4c5d01
commit 74d165b18d
15 changed files with 503 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

47
src/mainboard/intel/d510mo/Kconfig Normal file
View File

@ -0,0 +1,47 @@
#
# This file is part of the coreboot project.
#
# Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
if BOARD_INTEL_D510MO
config BOARD_SPECIFIC_OPTIONS
def_bool y
select CPU_INTEL_SOCKET_FCBGA559
select NORTHBRIDGE_INTEL_PINEVIEW
select SOUTHBRIDGE_INTEL_I82801GX
select SUPERIO_WINBOND_W83627THG
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_1024
config MAX_CPUS
int
default 4
config MMCONF_BASE_ADDRESS
hex
default 0xe0000000
config CBFS_SIZE
hex "Size of CBFS filesystem in ROM"
default 0x100000
config MAINBOARD_DIR
string
default intel/d510mo
config MAINBOARD_PART_NUMBER
string
default "D510MO"
endif # BOARD_INTEL_D510MO

2
src/mainboard/intel/d510mo/Kconfig.name Normal file
View File

@ -0,0 +1,2 @@
config BOARD_INTEL_D510MO
bool "D510MO"

1
src/mainboard/intel/d510mo/Makefile.inc Normal file
View File

@ -0,0 +1 @@
ramstage-y += cstates.c

1
src/mainboard/intel/d510mo/acpi/ec.asl Normal file
View File

@ -0,0 +1 @@
/* dummy */

35
src/mainboard/intel/d510mo/acpi/ich7_pci_irqs.asl Normal file
View File

@ -0,0 +1,35 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* This is board specific information:
* IRQ routing for the 0:1e.0 PCI bridge of the ICH7
*/
If (PICM) {
Return (Package() {
Package() { 0x0000ffff, 0, 0, 22},
Package() { 0x0000ffff, 1, 0, 20},
Package() { 0x0000ffff, 2, 0, 17},
Package() { 0x0000ffff, 3, 0, 16},
})
} Else {
Return (Package() {
Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKG, 0},
Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKE, 0},
Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKB, 0},
Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKA, 0},
})
}

72
src/mainboard/intel/d510mo/acpi/pineview_pci_irqs.asl Normal file
View File

@ -0,0 +1,72 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* This is board specific information: IRQ routing for pineview */
/* FIXME: EHCI controller not working yet */
/* PCI Interrupt Routing */
Method(_PRT)
{
If (PICM) {
Return (Package() {
/* Internal GFX */
Package() { 0x0002ffff, 0, 0, 16 },
/* High Definition Audio 0:1b.0 */
Package() { 0x001bffff, 0, 0, 22 },
/* PCIe Root Ports 0:1c.x */
Package() { 0x001cffff, 0, 0, 17 },
Package() { 0x001cffff, 1, 0, 16 },
Package() { 0x001cffff, 2, 0, 18 },
Package() { 0x001cffff, 3, 0, 19 },
/* USB and EHCI 0:1d.x */
Package() { 0x001dffff, 0, 0, 23 },
Package() { 0x001dffff, 1, 0, 19 },
Package() { 0x001dffff, 2, 0, 18 },
Package() { 0x001dffff, 3, 0, 16 },
Package() { 0x001dffff, 0, 0, 23 },
/* PCI 0:1e.0 */
Package() { 0x001effff, 0, 0, 22 },
/* LPC/SATA/SMBUS 0:1f.2, 0:1f.3 */
Package() { 0x001fffff, 1, 0, 19 },
Package() { 0x001fffff, 1, 0, 19 },
Package() { 0x001fffff, 1, 0, 19 },
})
} Else {
Return (Package() {
/* Internal GFX */
Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
/* High Definition Audio 0:1b.0 */
Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
/* PCIe Root Ports 0:1c.x */
Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKA, 0 },
Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
/* USB and EHCI 0:1d.x */
Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
/* PCI 0:1e.0 */
Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
/* LPC/SATA/SMBUS 0:1f.2, 0:1f.3 */
Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
})
}
}

1
src/mainboard/intel/d510mo/acpi/superio.asl Normal file
View File

@ -0,0 +1 @@
/* dummy */

21
src/mainboard/intel/d510mo/acpi_tables.c Normal file
View File

@ -0,0 +1,21 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <types.h>
#include <southbridge/intel/i82801gx/nvs.h>
void acpi_create_gnvs(global_nvs_t *gnvs)
{
}

5
src/mainboard/intel/d510mo/board_info.txt Normal file
View File

@ -0,0 +1,5 @@
Category: desktop
Board URL: http://www.intel.com/p/en_US/support/highlights/dsktpboards/d510mo
ROM package: SOIC-8
ROM protocol: SPI
ROM socketed: n

7
src/mainboard/intel/d510mo/cstates.c Normal file
View File

@ -0,0 +1,7 @@
#include <device/device.h>
#include <arch/x86/include/arch/acpigen.h>
int get_cst_entries(acpi_cstate_t **entries)
{
return 0;
}

94
src/mainboard/intel/d510mo/devicetree.cb Normal file
View File

@ -0,0 +1,94 @@
#
# This file is part of the coreboot project.
#
# Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
chip northbridge/intel/pineview # Northbridge
device cpu_cluster 0 on # APIC cluster
chip cpu/intel/socket_FCBGA559 # CPU
device lapic 0 on end # APIC
end
end
device domain 0 on # PCI domain
device pci 0.0 on end # Host Bridge
device pci 2.0 off end # Integrated graphics controller
chip southbridge/intel/i82801gx # Southbridge
register "pirqa_routing" = "0x0b"
register "pirqb_routing" = "0x0b"
register "pirqc_routing" = "0x0b"
register "pirqd_routing" = "0x0b"
register "pirqe_routing" = "0x0b"
register "pirqf_routing" = "0x0b"
register "pirqg_routing" = "0x0b"
register "pirqh_routing" = "0x0b"
register "ide_legacy_combined" = "0x1"
register "ide_enable_primary" = "0x1"
register "ide_enable_secondary" = "0x0"
register "sata_ahci" = "0x0"
device pci 1b.0 on end # Audio
device pci 1c.0 on end # PCIe 1
device pci 1c.1 on end # PCIe 2
device pci 1c.2 on end # PCIe 3
device pci 1c.3 on end # PCIe 4
device pci 1d.0 on end # USB
device pci 1d.1 on end # USB
device pci 1d.2 on end # USB
device pci 1d.3 on end # USB
device pci 1d.7 on end # USB
device pci 1e.0 on end # PCI bridge
device pci 1f.0 on # ISA bridge
chip superio/winbond/w83627thg # Super I/O
device pnp 4e.0 off end # Floppy
device pnp 4e.1 on # Parallel port
io 0x60 = 0x378
irq 0x70 = 7
drq 0x74 = 4
end
device pnp 4e.2 on # COM1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 4e.3 on # COM2
io 0x60 = 0x2f8
irq 0x70 = 3
irq 0xf1 = 0
end
device pnp 4e.5 on # PS/2 keyboard / mouse
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1 # PS/2 keyboard interrupt
irq 0x72 = 12 # PS/2 mouse interrupt
irq 0xf0 = 0x80
end
device pnp 4e.6 off end
device pnp 4e.7 off end
device pnp 4e.8 off end
device pnp 4e.9 off end
device pnp 4e.a off end # ACPI
device pnp 4e.b on # HWM
io 0x60 = 0x290
irq 0x70 = 0
end
end
end
device pci 1f.1 off end
device pci 1f.2 on end # SATA
device pci 1f.3 on end # SMbus
device pci 1f.4 off end
device pci 1f.5 off end
device pci 1f.6 off end
end
end
end

38
src/mainboard/intel/d510mo/dsdt.asl Normal file
View File

@ -0,0 +1,38 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
DefinitionBlock(
"dsdt.aml",
"DSDT",
0x02, // DSDT revision: ACPI v2.0
"COREv4", // OEM id
"COREBOOT", // OEM table id
0x20090419 // OEM revision
)
{
#include <southbridge/intel/i82801gx/acpi/globalnvs.asl>
Scope (\_SB) {
Device (PCI0)
{
#include <northbridge/intel/pineview/acpi/pineview.asl>
#include <southbridge/intel/i82801gx/acpi/ich7.asl>
}
}
/* Chipset specific sleep states */
#include <southbridge/intel/i82801gx/acpi/sleepstates.asl>
}

7
src/mainboard/intel/d510mo/hda_verb.c Normal file
View File

@ -0,0 +1,7 @@
#include <device/azalia_device.h>
const u32 cim_verb_data[0] = {};
const u32 pc_beep_verbs[0] = {};
AZALIA_ARRAY_SIZES;

36
src/mainboard/intel/d510mo/mainboard.c Normal file
View File

@ -0,0 +1,36 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/device.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <drivers/intel/gma/i915.h>
#include <pc80/mc146818rtc.h>
#include <device/pci.h>
const struct i915_gpu_controller_info *
intel_gma_get_controller_info(void)
{
return NULL;
}
static void mainboard_enable(device_t dev)
{
dev->ops->init = NULL;
}
struct chip_operations mainboard_ops = {
.enable_dev = mainboard_enable,
};

136
src/mainboard/intel/d510mo/romstage.c Normal file
View File

@ -0,0 +1,136 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdint.h>
#include <stdlib.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <console/console.h>
#include <southbridge/intel/i82801gx/i82801gx.h>
#include <northbridge/intel/pineview/raminit.h>
#include <northbridge/intel/pineview/pineview.h>
#include <cpu/x86/bist.h>
#include <cpu/x86/lapic.h>
#include <superio/winbond/w83627thg/w83627thg.h>
#include <superio/winbond/common/winbond.h>
#include <lib.h>
#include <arch/stages.h>
#define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1)
#define SUPERIO_DEV PNP_DEV(0x4e, 0)
#include <cpu/intel/romstage.h>
/* Early mainboard specific GPIO setup */
static void mb_gpio_init(void)
{
device_t dev;
/* Southbridge GPIOs. */
dev = PCI_DEV(0x0, 0x1f, 0x0);
/* Set the value for GPIO base address register and enable GPIO. */
pci_write_config32(dev, GPIO_BASE, (DEFAULT_GPIOBASE | 1));
pci_write_config8(dev, GPIO_CNTL, 0x10);
outl(0x1ff9f7c1, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */
outl(0xe0e9e803, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */
outl(0xece9e842, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
outl(0x00002000, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */
outl(0x000000fe, DEFAULT_GPIOBASE + 0x30);
outl(0x0000007e, DEFAULT_GPIOBASE + 0x34);
outl(0x000300f3, DEFAULT_GPIOBASE + 0x38);
}
static void nm10_enable_lpc(void)
{
/* Disable Serial IRQ */
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0x00);
/* Decode range */
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80,
pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x80) | 0x0010);
pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN,
CNF1_LPC_EN | CNF2_LPC_EN | KBC_LPC_EN | COMA_LPC_EN | COMB_LPC_EN);
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x88, 0x0291);
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8a, 0x007c);
}
static void rcba_config(void)
{
/* Set up virtual channel 0 */
RCBA32(0x0014) = 0x80000001;
RCBA32(0x001c) = 0x03128010;
/* Device 1f interrupt pin register */
RCBA32(0x3100) = 0x00042210;
RCBA32(0x3108) = 0x10004321;
RCBA32(0x3104) = 0x00002100;
/* PCIe Interrupts */
RCBA32(0x310c) = 0x00214321;
/* HD Audio Interrupt */
RCBA32(0x3110) = 0x00000001;
/* dev irq route register */
RCBA16(0x3140) = 0x0132;
RCBA16(0x3142) = 0x0146;
RCBA16(0x3144) = 0x0237;
RCBA16(0x3146) = 0x3201;
RCBA16(0x3148) = 0x0146;
/* Enable IOAPIC */
RCBA8(0x31ff) = 0x03;
RCBA32(0x3418) = 0x003000e2;
RCBA32(0x3418) |= 1;
}
void main(unsigned long bist)
{
const u8 spd_addrmap[4] = { 0x50, 0x51, 0, 0 };
if (bist == 0)
enable_lapic();
/* Disable watchdog timer */
RCBA32(0x3410) = RCBA32(0x3410) | 0x20;
/* Set southbridge and Super I/O GPIOs. */
mb_gpio_init();
nm10_enable_lpc();
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
report_bist_failure(bist);
enable_smbus();
pineview_early_initialization();
post_code(0x30);
printk(BIOS_DEBUG, "Start native raminit\n");
sdram_initialize(0, spd_addrmap);
printk(BIOS_DEBUG, "Native raminit done\n");
post_code(0x31);
ram_check(0x200000,0x300000);
rcba_config();
}