soc/intel/skylake: Add devicetree variable for PCIe HotPlug

Add a variable to fill out the FSP UPD variable for PCIe HotPlug,
which allows a mainboard to enable HotPlug on individual root ports.

BUG=b:72417777
TEST=enable HotPlug on Eve Root Port 0 (WiFi) and check in linux
that it is identified as a HotPlug capable root port.

Change-Id: I6b1f525e41909a3f81984806c4ef20239032c8d6
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/23511
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/skylake/chip.c

@@ -121,6 +121,8 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
 			sizeof(params->PcieRpClkReqSupport));
 	memcpy(params->PcieRpClkReqNumber, config->PcieRpClkReqNumber,
 			sizeof(params->PcieRpClkReqNumber));
+	memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug,
+			sizeof(params->PcieRpHotPlug));
 
 	params->EnableLan = config->EnableLan;
 	params->Cio2Enable = config->Cio2Enable;

src/soc/intel/skylake/chip.h

@@ -231,6 +231,9 @@ struct soc_intel_skylake_config {
 	 */
 	u8 PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS];
 
+	/* Enable/Disable HotPlug support for Root Port */
+	u8 PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS];
+
 	/* USB related */
 	struct usb2_port_config usb2_ports[16];
 	struct usb3_port_config usb3_ports[10];

src/soc/intel/skylake/chip_fsp20.c

@@ -170,6 +170,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 			sizeof(params->PcieRpAdvancedErrorReporting));
 	memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable,
 	       sizeof(params->PcieRpLtrEnable));
+	memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug,
+	       sizeof(params->PcieRpHotPlug));
 
 	/*
 	 * PcieRpClkSrcNumber UPD is set to clock source number(0-6) for