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soc/intel/common: register generic LPC resources 

Register the generic LPC memory/IO ranges with the resource allocator.

TEST: set ranges and check the coreboot log

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I9f45b38498390016f841ab1d70c8438496dc857e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Michael Niewöhner 2022-04-03 21:00:45 +02:00 committed by Felix Held
parent 95af254e11
commit 74ec3efcad
1 changed files with 32 additions and 0 deletions
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32
src/soc/intel/common/block/lpc/lpc.c
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@ -6,6 +6,8 @@
#include <intelblocks/lpc_lib.h> #include <intelblocks/lpc_lib.h>
#include <soc/pm.h> #include <soc/pm.h>
#include "lpc_def.h"
/* SoC overrides */ /* SoC overrides */
/* Common weak definition, needs to be implemented in each soc LPC driver. */ /* Common weak definition, needs to be implemented in each soc LPC driver. */
@ -32,14 +34,41 @@ void pch_lpc_add_new_resource(struct device *dev, uint8_t offset,
static void pch_lpc_add_io_resources(struct device *dev) static void pch_lpc_add_io_resources(struct device *dev)
{ {
uint32_t gen_io_dec;
uint16_t base, size;
/* Add the default claimed legacy IO range for the LPC device. */ /* Add the default claimed legacy IO range for the LPC device. */
pch_lpc_add_new_resource(dev, 0, 0, 0x1000, IORESOURCE_IO | pch_lpc_add_new_resource(dev, 0, 0, 0x1000, IORESOURCE_IO |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED); IORESOURCE_ASSIGNED | IORESOURCE_FIXED);
/* LPC Generic IO Decode ranges */
for (size_t i = 0; i < LPC_NUM_GENERIC_IO_RANGES; i++) {
gen_io_dec = pci_read_config32(dev, LPC_GENERIC_IO_RANGE(i));
if (gen_io_dec & LPC_LGIR_EN) {
base = gen_io_dec & LPC_LGIR_ADDR_MASK;
size = (0x3 | ((gen_io_dec >> 16) & 0xfc)) + 1;
pch_lpc_add_new_resource(dev, LPC_GENERIC_IO_RANGE(i), base, size,
IORESOURCE_IO | IORESOURCE_ASSIGNED |
IORESOURCE_FIXED);
}
}
/* SoC IO resource overrides */ /* SoC IO resource overrides */
pch_lpc_soc_fill_io_resources(dev); pch_lpc_soc_fill_io_resources(dev);
} }
static void pch_lpc_add_mmio_resources(struct device *dev)
{
/* LPC Memory Decode */
uint32_t lgmr = pci_read_config32(dev, LPC_GENERIC_MEM_RANGE);
if (lgmr & LPC_LGMR_EN) {
lgmr &= LPC_LGMR_ADDR_MASK;
pch_lpc_add_new_resource(dev, LPC_GENERIC_MEM_RANGE, lgmr, LPC_LGMR_WINDOW_SIZE,
IORESOURCE_MEM | IORESOURCE_ASSIGNED |
IORESOURCE_FIXED | IORESOURCE_RESERVE);
}
}
static void pch_lpc_read_resources(struct device *dev) static void pch_lpc_read_resources(struct device *dev)
{ {
/* Get the PCI resources of this device. */ /* Get the PCI resources of this device. */
@ -47,6 +76,9 @@ static void pch_lpc_read_resources(struct device *dev)
/* Add IO resources to LPC. */ /* Add IO resources to LPC. */
pch_lpc_add_io_resources(dev); pch_lpc_add_io_resources(dev);
/* Add non-standard MMIO resources. */
pch_lpc_add_mmio_resources(dev);
} }
static void pch_lpc_set_child_resources(struct device *dev); static void pch_lpc_set_child_resources(struct device *dev);