cpu/intel/car/non-evict: Select NO_FIXED_XIP_ROM_SIZE

CPU's featuring a non eviction mode cache the whole ROM.
Therefore XIP stages don't need to follow some alignment constraints.

Change-Id: I4a30f31baa0f90279c0690ceb6aefea6de461bd9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

src/cpu/intel/haswell/Kconfig

@@ -23,6 +23,7 @@ config CPU_SPECIFIC_OPTIONS
 	select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
 	select PARALLEL_MP
 	select CPU_INTEL_COMMON
+	select NO_FIXED_XIP_ROM_SIZE
 
 config SMM_TSEG_SIZE
 	hex

src/cpu/intel/model_2065x/Kconfig

@@ -19,6 +19,7 @@ config CPU_SPECIFIC_OPTIONS
 	#select AP_IN_SIPI_WAIT
 	select TSC_SYNC_MFENCE
 	select CPU_INTEL_COMMON
+	select NO_FIXED_XIP_ROM_SIZE
 
 config BOOTBLOCK_CPU_INIT
 	string
@@ -28,8 +29,4 @@ config SMM_TSEG_SIZE
 	hex
 	default 0x800000
 
-config XIP_ROM_SIZE
-	hex
-	default 0x20000
-
 endif

src/cpu/intel/model_206ax/Kconfig

@@ -25,15 +25,12 @@ config CPU_SPECIFIC_OPTIONS
 	select CPU_INTEL_COMMON
 	select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
 	select PARALLEL_MP
+	select NO_FIXED_XIP_ROM_SIZE
 
 config BOOTBLOCK_CPU_INIT
 	string
 	default "cpu/intel/model_206ax/bootblock.c"
 
-config XIP_ROM_SIZE
-	hex
-	default 0x20000 if USE_NATIVE_RAMINIT
-
 config SMM_TSEG_SIZE
 	hex
 	default 0x800000

src/cpu/intel/socket_FCBGA559/Kconfig

@@ -11,6 +11,7 @@ config SOCKET_SPECIFIC_OPTIONS
 	select MMX
 	select SSE
 	select CPU_HAS_L2_ENABLE_MSR
+	select NO_FIXED_XIP_ROM_SIZE
 
 config DCACHE_RAM_BASE
 	hex

src/soc/intel/broadwell/Kconfig

@@ -43,6 +43,7 @@ config CPU_SPECIFIC_OPTIONS
 	select POSTCAR_CONSOLE
 	select HAVE_POWER_STATE_AFTER_FAILURE
 	select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
+	select NO_FIXED_XIP_ROM_SIZE
 
 config PCIEXP_ASPM
 	bool