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kunimitsu: Update Serial IO modes in devicetree 

This patch updates the Serial IO modes for UART 1 and 2
in devicetree for kunimitsu boards.
UART1 are disabled and
UART2 is in PCI mode.

BRANCH=None
BUG=chrome-os-partner:40857
TEST=Built for kunimitsu and tested LPSS logs on Kunimitsu.

Change-Id: I5a46ab9e0b792478ee2e0845aeab1443423a2fac
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 38c7b963a9d679ee5106c5343e1173d0b5056627
Original-Change-Id: I39cbb6bb0991e5f9b3365adaf6b24818d112cd1a
Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/284825
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Wenkai Du <wenkai.du@intel.com>
Original-Tested-by: Wenkai Du <wenkai.du@intel.com>
Reviewed-on: http://review.coreboot.org/11001
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Naveen Krishna Chatradhi 2015-07-09 18:00:40 +05:30 committed by Patrick Georgi
parent baf4e3e92d
commit 75154b801f
1 changed files with 1 additions and 1 deletions
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2
src/mainboard/intel/kunimitsu/devicetree.cb
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@ -12,7 +12,7 @@ chip soc/intel/skylake
[PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \
[PchSerialIoIndexUart0] = PchSerialIoPci, \ [PchSerialIoIndexUart0] = PchSerialIoPci, \
[PchSerialIoIndexUart1] = PchSerialIoDisabled, \ [PchSerialIoIndexUart1] = PchSerialIoDisabled, \
[PchSerialIoIndexUart2] = PchSerialIoLegacyUart, \ [PchSerialIoIndexUart2] = PchSerialIoPci, \
}" }"
register "pirqa_routing" = "0x8b" register "pirqa_routing" = "0x8b"