From 75178071fb852970485b8bfe5a151a153f446792 Mon Sep 17 00:00:00 2001 From: Werner Zeh Date: Wed, 21 Jul 2021 07:26:38 +0200 Subject: [PATCH] mb/siemens/mc_ehl1: Disable power management features for SATA Features like DevSLP and Aggressive Link Power Management are not supported on this mainboard and are therefore disabled. Change-Id: I3bc650ea78be8587889fb7abfe7075cd9a122198 Signed-off-by: Werner Zeh Reviewed-on: https://review.coreboot.org/c/coreboot/+/56486 Tested-by: build bot (Jenkins) Reviewed-by: Mario Scheithauer Reviewed-by: Paul Menzel --- src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb index 4da94d9734..d08ac368a4 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb @@ -64,11 +64,11 @@ chip soc/intel/elkhartlake register "PcieClkSrcClkReq[5]" = "0xFF" # Storage (SATA/SDCARD/EMMC) related UPDs - register "SataSalpSupport" = "1" + register "SataSalpSupport" = "0" register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "1" register "SataPortsDevSlp[0]" = "0" - register "SataPortsDevSlp[1]" = "1" + register "SataPortsDevSlp[1]" = "0" register "ScsEmmcHs400Enabled" = "1" register "ScsEmmcDdr50Enabled" = "1"