arch/x86: Move prologue to .init section

For arch/x86 the realmode part has to be located within the same 64
KiB as the reset vector. Some older intel platforms also require 4 KiB
alignment for _start16bit.

To enforce the above, and to separate required parts of .text without
matching *(.text.*) rules in linker scripts, tag the pre-C environment
assembly code with section .init directive.

Description of .init section for ELF:

This section holds executable instructions that contribute to the
process initialization code. When a program starts to run, the
system arranges to execute the code in this section before calling the
main program entry point (called main for C programs).

Change-Id: If32518b1c19d08935727330314904b52a246af3c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47599
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/arch/x86/bootblock_crt0.S

@@ -10,7 +10,7 @@
 
 #include <cpu/x86/cr.h>
 
-.section .text._start
+.section .init._start, "ax", @progbits
 
 /*
  * Include the old code for reset vector and protected mode entry. That code has

src/arch/x86/gdt_init.S

@@ -1,7 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 .code32
-.section ".text._gdt_", "ax", @progbits
+
+.section .init, "ax", @progbits
+
+.section .init._gdt_, "ax", @progbits
 
 	.globl gdt_init
 gdt_init:
@@ -17,7 +20,7 @@ gdtptr:
 
 #ifdef __x86_64__
 .code64
-.section ".text._gdt64_", "ax", @progbits
+.section .init._gdt64_, "ax", @progbits
 	.globl gdt_init64
 gdt_init64:
 	/* Workaround a bug in the assembler.

src/arch/x86/walkcbfs.S

@@ -21,7 +21,7 @@
 #define CBFS_FILE_STRUCTSIZE (CBFS_FILE_OFFSET + 4)
 
 .code32
-.section .text
+.section .init
 .global walkcbfs_asm
 
 /*

src/cpu/intel/car/core2/cache_as_ram.S

@@ -4,6 +4,7 @@
 #include <cpu/x86/cache.h>
 #include <cpu/x86/post_code.h>
 
+.section .init
 .global bootblock_pre_c_entry
 
 .code32

src/cpu/intel/car/non-evict/cache_as_ram.S

@@ -7,6 +7,7 @@
 #define NoEvictMod_MSR 0x2e0
 #define BBL_CR_CTL3_MSR 0x11e
 
+.section .init
 .global bootblock_pre_c_entry
 
 #include <cpu/intel/car/cache_as_ram_symbols.inc>

src/cpu/intel/car/p3/cache_as_ram.S

@@ -4,6 +4,7 @@
 #include <cpu/x86/cache.h>
 #include <cpu/x86/post_code.h>
 
+.section .init
 .global bootblock_pre_c_entry
 
 .code32

src/cpu/intel/car/p4-netburst/cache_as_ram.S

@@ -8,6 +8,7 @@
 /* Macro to access Local APIC registers at default base. */
 #define LAPIC(x)		$(LAPIC_DEFAULT_BASE | LAPIC_ ## x)
 
+.section .init
 .global bootblock_pre_c_entry
 
 .code32

src/cpu/intel/microcode/microcode_asm.S

@@ -44,7 +44,7 @@
  */
 
 .code32
-.section .text
+.section .init
 .global update_bsp_microcode
 
 update_bsp_microcode:

src/cpu/qemu-x86/cache_as_ram_bootblock.S

@@ -2,6 +2,8 @@
 
 #include <cpu/x86/post_code.h>
 
+.section .init, "ax", @progbits
+
 .global bootblock_pre_c_entry
 bootblock_pre_c_entry:
 

src/drivers/amd/agesa/cache_as_ram.S

@@ -10,16 +10,19 @@
  ******************************************************************************
  */
 
-#include "gcccar.inc"
 #include <cpu/x86/lapic_def.h>
 #include <cpu/x86/post_code.h>
 
+.section .init
+
 .code32
-.globl _cache_as_ram_setup, _cache_as_ram_setup_end
+
 .global bootblock_pre_c_entry
 
 _cache_as_ram_setup:
 
+#include "gcccar.inc"
+
 /*
  * on entry:
  *   mm0: BIST (ignored)

src/drivers/intel/fsp1_1/cache_as_ram.S

@@ -14,6 +14,8 @@
 
 #define LHLT_DELAY	0x50000	/* I/O delay between post codes on failure */
 
+.section .init, "ax", @progbits
+
 .global	bootblock_pre_c_entry
 bootblock_pre_c_entry:
 	/*

src/lib/program.ld

@@ -13,6 +13,9 @@
 .text . : {
 	_program = .;
 	_text = .;
+	*(.init._start);
+	*(.init);
+	*(.init.*);
 	*(.text._start);
 	*(.text.stage_entry);
 	KEEP(*(.metadata_hash_anchor));

src/soc/amd/common/block/cpu/car/cache_as_ram.S

@@ -8,9 +8,16 @@
  ******************************************************************************
  */
 
-#include "gcccar.inc"
 #include <cpu/x86/post_code.h>
 
+.section .init
+
+.code32
+
+_cache_as_ram_setup:
+
+#include "gcccar.inc"
+
 /*
  * on entry:
  *   mm0: BIST (ignored)
@@ -43,3 +50,5 @@ before_carstage:
 	post_code(POST_DEAD_CODE)
 	hlt
 	jmp	.halt_forever
+
+_cache_as_ram_setup_end:

src/soc/amd/common/block/cpu/noncar/pre_c.S

@@ -2,6 +2,8 @@
 
 #include <cpu/x86/post_code.h>
 
+.section .init, "ax", @progbits
+
 .global bootblock_resume_entry
 bootblock_resume_entry:
 	post_code(0xb0)

src/soc/example/min86/cache_as_ram.S

@@ -1,5 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+.section .init, "ax", @progbits
+
 .global bootblock_pre_c_entry
 
 .code32

src/soc/intel/common/block/cpu/car/cache_as_ram.S

@@ -9,6 +9,8 @@
 #include <rules.h>
 #include <intelblocks/msr.h>
 
+.section .init, "ax", @progbits
+
 .code32
 .global bootblock_pre_c_entry
 bootblock_pre_c_entry:

src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S

@@ -10,6 +10,8 @@
 #define CBFS_FILE_CHECKSUM (CBFS_FILE_TYPE + 4)
 #define CBFS_FILE_OFFSET (CBFS_FILE_CHECKSUM + 4)
 
+.section .init, "ax", @progbits
+
 .extern	temp_ram_init_params
 
 .global	bootblock_pre_c_entry

src/soc/intel/quark/bootblock/esram_init.S

@@ -71,6 +71,8 @@
 .equ  CFGNONSTICKY_W1_OFFSET, (0x52)
 .equ    FORCE_WARM_RESET, (0x00000001)
 
+.section .init, "ax", @progbits
+
 	.global bootblock_pre_c_entry
 
 bootblock_pre_c_entry: