uart/sifive: make divisor configurable
The SiFive UART on the HiFive Unleashed uses the tlclk as input clock which runs at coreclk / 2. The input frequency is configured in the board code depending on the current stage. (bootblock + romstage run at 33.33Mhz, ramstage at 1Ghz) Change-Id: Iaf66723dba3d308f809fde5b05dfc3e43f43bd42 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/27440 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
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@ -46,11 +46,10 @@ struct sifive_uart_registers {
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#define IP_TXWM BIT(0)
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#define IP_RXWM BIT(1)
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void uart_init(int idx)
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static void sifive_uart_init(struct sifive_uart_registers *regs, int div)
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{
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struct sifive_uart_registers *regs = uart_platform_baseptr(idx);
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/* TODO: Configure the divisor */
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/* Configure the divisor */
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write32(®s->div, div);
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/* Enable transmission, one stop bit, transmit watermark at 1 */
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write32(®s->txctrl, TXCTRL_TXEN|TXCTRL_NSTOP(1)|TXCTRL_TXCNT(1));
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@ -59,6 +58,14 @@ void uart_init(int idx)
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write32(®s->rxctrl, RXCTRL_RXEN|RXCTRL_RXCNT(0));
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}
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void uart_init(int idx)
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{
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unsigned int div;
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div = uart_baudrate_divisor(get_uart_baudrate(),
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uart_platform_refclk(), uart_input_clock_divider());
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sifive_uart_init(uart_platform_baseptr(idx), div);
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}
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static bool uart_can_tx(struct sifive_uart_registers *regs)
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{
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return !(read32(®s->txdata) & TXDATA_FULL);
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@ -20,7 +20,7 @@ config SOC_SIFIVE_FU540
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select ARCH_RAMSTAGE_RISCV
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select BOOTBLOCK_CONSOLE
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select DRIVERS_UART_SIFIVE
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select UART_OVERRIDE_REFCLK
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if SOC_SIFIVE_FU540
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config RISCV_ARCH
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@ -23,3 +23,11 @@ uintptr_t uart_platform_base(int idx)
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else
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return 0;
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}
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unsigned int uart_platform_refclk(void)
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{
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/*
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* The SiFive UART uses tlclk, which is coreclk/2 as input
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*/
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return 33330000 / 2;
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}
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