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soc/intel/apollolake: Rename SRAM BAR0 and BAR2 macros

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Rename BAR0 and BAR2 SRAM base and size macros to align with the spec.
* PMC_SRAM_BASE_0 -> SRAM_BASE_0
* PMC_SRAM_SIZE_0 -> SRAM_SIZE_0
* PMC_SRAM_BASE_1 -> SRAM_BASE_2
* PMC_SRAM_SIZE_1 -> SRAM_SIZE_2

Change-Id: I48d65c30368c4500549b535341b14ca262d7fc48
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/20539
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
V Sowmya 2017-07-12 14:27:09 +05:30 committed by Aaron Durbin
parent 1e6b980b1e
commit 752dc8e425
3 changed files with 10 additions and 10 deletions
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2
src/soc/intel/apollolake/acpi/pmc_ipc.asl
View file

@ -52,7 +52,7 @@ scope (\_SB) {
Store (MCH_BASE_ADDRESS + MAILBOX_INTF, MIBA)
CreateDwordField (^RBUF, ^SBAR._BAS, SBAS)
Store (PMC_SRAM_BASE_0, SBAS)
Store (SRAM_BASE_0, SBAS)
Return (^RBUF)
}

8
src/soc/intel/apollolake/include/soc/iomap.h
View file

@ -39,10 +39,10 @@
#define PMC_BAR1 0xfe044000
#define PMC_BAR0_SIZE (8 * KiB)
#define PMC_SRAM_BASE_0 0xfe900000
#define PMC_SRAM_SIZE_0 (8 * KiB)
#define PMC_SRAM_BASE_1 0xfe902000
#define PMC_SRAM_SIZE_1 (4 * KiB)
#define SRAM_BASE_0 0xfe900000
#define SRAM_SIZE_0 (8 * KiB)
#define SRAM_BASE_2 0xfe902000
#define SRAM_SIZE_2 (4 * KiB)
/* Temporary BAR for SPI until PCI enumeration assigns a BAR in ramstage. */
#define PRERAM_SPI_BASE_ADDRESS 0xfe010000

10
src/soc/intel/apollolake/sram.c
View file

@ -26,13 +26,13 @@ static void read_resources(device_t dev)
pci_dev_read_resources(dev);
res = new_resource(dev, PCI_BASE_ADDRESS_0);
res->base = PMC_SRAM_BASE_0;
res->size = PMC_SRAM_SIZE_0;
res->base = SRAM_BASE_0;
res->size = SRAM_SIZE_0;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, PCI_BASE_ADDRESS_2);
res->base = PMC_SRAM_BASE_1;
res->size = PMC_SRAM_SIZE_1;
res->base = SRAM_BASE_2;
res->size = SRAM_SIZE_2;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
@ -51,7 +51,7 @@ static void set_resources(device_t dev)
pci_write_config32(dev, res->index, res->base);
dev->command |= PCI_COMMAND_MEMORY;
res->flags |= IORESOURCE_STORED;
report_resource_stored(dev, res, " SRAM BAR 1");
report_resource_stored(dev, res, " SRAM BAR 2");
}
static const struct device_operations device_ops = {