diff --git a/src/cpu/amd/model_10xxx/defaults.h b/src/cpu/amd/model_10xxx/defaults.h
index 78c46d4eaf..bddeb7c0f7 100644
--- a/src/cpu/amd/model_10xxx/defaults.h
+++ b/src/cpu/amd/model_10xxx/defaults.h
@@ -136,27 +136,27 @@ static const struct {
 	 * program Link Global Extended Control Register[ForceFullT0]
 	 * (F0x16C[15:13]) to 000b */
 
-	{ 0, 0x170, AMD_FAM10_ALL, AMD_PTYPE_ALL, /* Fix FAM10_ALL when fixed in rev guide */
+	{ 0, 0x170, AMD_DRBA23_RBC2, AMD_PTYPE_ALL, /* FIXME Should include BL_C2 but there is no constant */
 	  0x00000000, 0x00000100 },
-	{ 0, 0x174, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+	{ 0, 0x174,  AMD_DRBA23_RBC2, AMD_PTYPE_ALL,
 	  0x00000000, 0x00000100 },
-	{ 0, 0x178, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+	{ 0, 0x178,  AMD_DRBA23_RBC2, AMD_PTYPE_ALL,
 	  0x00000000, 0x00000100 },
-	{ 0, 0x17C, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+	{ 0, 0x17C,  AMD_DRBA23_RBC2, AMD_PTYPE_ALL,
 	  0x00000000, 0x00000100 },
-	{ 0, 0x180, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+	{ 0, 0x180,  AMD_DRBA23_RBC2, AMD_PTYPE_ALL,
 	  0x00000000, 0x00000100 },
-	{ 0, 0x184, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+	{ 0, 0x184,  AMD_DRBA23_RBC2, AMD_PTYPE_ALL,
 	  0x00000000, 0x00000100 },
-	{ 0, 0x188, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+	{ 0, 0x188,  AMD_DRBA23_RBC2, AMD_PTYPE_ALL,
 	  0x00000000, 0x00000100 },
-	{ 0, 0x18C, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+	{ 0, 0x18C,  AMD_DRBA23_RBC2, AMD_PTYPE_ALL,
 	  0x00000000, 0x00000100 },
-	{ 0, 0x170, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+	{ 0, 0x170,  AMD_DRBA23_RBC2, AMD_PTYPE_ALL,
 	  0x00000000, 0x00000100 },
 
 	/* Link Global Extended Control Register */
-	{ 0, 0x16C, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+	{ 0, 0x16C,  AMD_DRBA23_RBC2, AMD_PTYPE_ALL,
 	  0x00000014, 0x0000003F },	/* [15:13] ForceFullT0 = 0b,
 								 * Set T0Time 14h per BKDG */
 
diff --git a/src/northbridge/amd/amdmct/amddefs.h b/src/northbridge/amd/amdmct/amddefs.h
index d72754690f..830f5e527b 100644
--- a/src/northbridge/amd/amdmct/amddefs.h
+++ b/src/northbridge/amd/amdmct/amddefs.h
@@ -62,10 +62,11 @@
 #define	AMD_DR_LT_B3	(AMD_DR_B0 | AMD_DR_B1 | AMD_DR_B2 | AMD_DR_BA)
 #define	AMD_DR_GT_B0	(AMD_DR_ALL & ~(AMD_DR_B0))
 #define	AMD_DR_ALL	(AMD_DR_Bx)
-#define	AMD_FAM10_ALL	(AMD_DR_ALL | AMD_RB_C2 | AMD_HY_D0 | AMD_DA_C3 | AMD_DA_C2)
+#define	AMD_FAM10_ALL	(AMD_DR_ALL | AMD_RB_C2 | AMD_HY_D0 | AMD_DA_C3 | AMD_DA_C2 | AMD_RB_C3 )
 #define	AMD_FAM10_GT_B0	(AMD_FAM10_ALL & ~(AMD_DR_B0))
 #define	AMD_DR_Cx       (AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3)
 #define	AMD_DR_Dx       (AMD_HY_D0)
+#define AMD_DRBA23_RBC2 (AMD_DR_BA | AMD_DR_B2 | AMD_DR_B3 | AMD_RB_C2 )
 
 
 /*