Kconfig builds all boards now.

This patch also aligns the configuration of a couple of
boards more closely to what newconfig does.

Also, the romstrap inc/lds files are declared in the
Makefiles of the southbridges they belong to, instead of
some global file.

AMD CPUs have their own timer functions, so disable UDELAY_IO
for them and set HAVE_INIT_TIMER as appropriate, same for
emulation/qemu-x86.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5000 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/arch/i386/Makefile.tinybootblock.inc

@@ -24,19 +24,14 @@ bootblock_lds := $(src)/arch/i386/init/ldscript_failover.lb
 bootblock_lds += $(src)/cpu/x86/16bit/entry16.lds
 bootblock_lds += $(src)/cpu/x86/16bit/reset16.lds
 bootblock_lds += $(src)/arch/i386/lib/id.lds
-ifeq ($(CONFIG_SOUTHBRIDGE_VIA_K8T890),y)
+bootblock_lds += $(chipset_bootblock_lds)
-bootblock_lds += $(src)/southbridge/via/k8t890/romstrap.lds
-endif
 
 bootblock_inc := $(src)/arch/i386/init/bootblock_prologue.c
 bootblock_inc += $(src)/cpu/x86/16bit/entry16.inc
 bootblock_inc += $(src)/cpu/x86/16bit/reset16.inc
 bootblock_inc += $(src)/cpu/x86/32bit/entry32.inc
 bootblock_inc += $(src)/arch/i386/lib/id.inc
-
+bootblock_inc += $(chipset_bootblock_inc)
-ifeq ($(CONFIG_SOUTHBRIDGE_VIA_K8T890),y)
-bootblock_inc += $(src)/southbridge/via/k8t890/romstrap.inc
-endif
 
 ifeq ($(CONFIG_SSE),y)
 bootblock_inc += $(src)/cpu/x86/sse_enable.inc

src/cpu/amd/model_10xxx/Kconfig

@@ -4,6 +4,7 @@ config CPU_AMD_MODEL_10XXX
 	select USE_PRINTK_IN_CAR
 	select USE_DCACHE_RAM
 	select SSE
+	select HAVE_INIT_TIMER
 
 config CPU_ADDR_BITS
 	int
@@ -25,3 +26,7 @@ config DCACHE_RAM_GLOBAL_VAR_SIZE
 	default 0x04000
 	depends on CPU_AMD_MODEL_10XXX
 
+config UDELAY_IO
+	bool
+	default n
+	depends on CPU_AMD_MODEL_10XXX

src/cpu/amd/model_fxx/Kconfig

@@ -4,6 +4,7 @@ config CPU_AMD_MODEL_FXX
 	select USE_PRINTK_IN_CAR
 	select USE_DCACHE_RAM
 	select SSE
+	select HAVE_INIT_TIMER
 
 config CPU_ADDR_BITS
 	int
@@ -25,3 +26,8 @@ config DCACHE_RAM_GLOBAL_VAR_SIZE
 	default 0x01000
 	depends on CPU_AMD_MODEL_FXX
 
+
+config UDELAY_IO
+	bool
+	default n
+	depends on CPU_AMD_MODEL_FXX

src/cpu/amd/sc520/Kconfig

@@ -1,3 +1,8 @@
 config CPU_AMD_SC520
 	bool
 
+config UDELAY_IO
+	bool
+	default n
+	depends on CPU_AMD_SC520
+

src/mainboard/emulation/qemu-x86/Kconfig

@@ -27,3 +27,8 @@ config HAVE_INIT_TIMER
 	bool
 	default n
 	depends on BOARD_EMULATION_QEMU_X86
+
+config UDELAY_IO
+	bool
+	default n
+	depends on BOARD_EMULATION_QEMU_X86

src/mainboard/supermicro/h8dmr_fam10/Kconfig

@@ -15,6 +15,8 @@ config BOARD_SUPERMICRO_H8DMR_FAM10
 	select LIFT_BSP_APIC_ID
 	select AMDMCT
 	select BOARD_ROMSIZE_KB_1024
+	select TINY_BOOTBLOCK
+	select ENABLE_APIC_EXT_ID
 
 config MAINBOARD_DIR
 	string
@@ -23,27 +25,42 @@ config MAINBOARD_DIR
 
 config DCACHE_RAM_BASE
 	hex
-	default 0xc8000
+	default 0xc4000
 	depends on BOARD_SUPERMICRO_H8DMR_FAM10
 
 config DCACHE_RAM_SIZE
 	hex
-	default 0x08000
+	default 0x0c000
 	depends on BOARD_SUPERMICRO_H8DMR_FAM10
 
 config DCACHE_RAM_GLOBAL_VAR_SIZE
 	hex
-	default 0x01000
+	default 0x04000
+	depends on BOARD_SUPERMICRO_H8DMR_FAM10
+
+config RAMBASE
+	hex
+	default 0x200000
+	depends on BOARD_SUPERMICRO_H8DMR_FAM10
+
+config RAMTOP
+	hex
+	default 0x1000000
+	depends on BOARD_SUPERMICRO_H8DMR_FAM10
+
+config HEAP_SIZE
+	hex
+	default 0xc0000
 	depends on BOARD_SUPERMICRO_H8DMR_FAM10
 
 config APIC_ID_OFFSET
 	hex
-	default 0x10
+	default 0x0
 	depends on BOARD_SUPERMICRO_H8DMR_FAM10
 
 config MEM_TRAIN_SEQ
 	int
-	default 1
+	default 2
 	depends on BOARD_SUPERMICRO_H8DMR_FAM10
 
 config SB_HT_CHAIN_ON_BUS0
@@ -78,7 +95,7 @@ config HW_MEM_HOLE_SIZEK
 
 config MAX_CPUS
 	int
-	default 4
+	default 8
 	depends on BOARD_SUPERMICRO_H8DMR_FAM10
 
 config MAX_PHYSICAL_CPUS
@@ -88,12 +105,12 @@ config MAX_PHYSICAL_CPUS
 
 config HT_CHAIN_END_UNITID_BASE
 	hex
-	default 0x0
+	default 0x20
 	depends on BOARD_SUPERMICRO_H8DMR_FAM10
 
 config HT_CHAIN_UNITID_BASE
 	hex
-	default 0x0
+	default 0x1
 	depends on BOARD_SUPERMICRO_H8DMR_FAM10
 
 config USE_INIT
@@ -115,3 +132,8 @@ config AMD_UCODE_PATCH_FILE
 	string
 	default "mc_patch_0100009f.h"
 	depends on BOARD_SUPERMICRO_H8DMR_FAM10
+
+config SERIAL_CPU_INIT
+	bool
+	default n
+	depends on BOARD_SUPERMICRO_H8DMR_FAM10

src/mainboard/supermicro/h8dmr_fam10/Makefile.inc

@@ -30,19 +30,12 @@ obj-$(CONFIG_GENERATE_PIRQ_TABLE) += irq_tables.o
 
 initobj-y += crt0.o
 # FIXME in $(top)/Makefile
-crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
 crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
-crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
-crt0-y += ../../../../src/arch/i386/lib/id.inc
-crt0-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.inc
 crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
 crt0-y += auto.inc
 
 ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
-ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
+ldscript-y += ../../../../src/cpu/x86/32bit/entry32.lds
-ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
-ldscript-y += ../../../../src/arch/i386/lib/id.lds
-ldscript-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.lds
 ldscript-y += ../../../../src/arch/i386/lib/failover.lds
 
 ifdef POST_EVALUATION
@@ -55,19 +48,19 @@ $(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
 	$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
 
 $(obj)/ssdt2.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci2.asl
-	iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl
+	iasl -p $(obj)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl
-	perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex
+	perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' $(obj)/pci2.hex
-	mv pci2.hex ssdt2.c
+	mv $(obj)/pci2.hex $(obj)/ssdt2.c
 
 $(obj)/ssdt3.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci3.asl"
-	iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/
+	iasl -p $(obj)/pci3 -tc $(CONFIG_MAINBOARD)/
-	perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex
+	perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' $(obj)/pci3.hex
-	mv pci3.hex ssdt3.c
+	mv $(obj)/pci3.hex $(obj)/ssdt3.c
 
 $(obj)/ssdt4.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci4.asl"
-	iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl
+	iasl -p $(obj)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl
-	perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex
+	perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' $(obj)/pci4.hex
-	mv pci4.hex ssdt4.c
+	mv $(obj)/pci4.hex $(obj)/ssdt4.c
 
 $(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h
 	$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S  $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@

src/mainboard/supermicro/h8dmr_fam10/devicetree.cb

@@ -1,5 +1,3 @@
-dir /southbridge/nvidia/mcp55
-
 chip northbridge/amd/amdfam10/root_complex
         device apic_cluster 0 on
                 chip cpu/amd/socket_F_1207

src/mainboard/tyan/s2912_fam10/Kconfig

@@ -13,10 +13,10 @@ config BOARD_TYAN_S2912_FAM10
 	select HAVE_HARD_RESET
 	select IOAPIC
 	select LIFT_BSP_APIC_ID
-	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
 	select BOARD_ROMSIZE_KB_1024
 	select ENABLE_APIC_EXT_ID
 	select AMDMCT
+	select TINY_BOOTBLOCK
 
 config MAINBOARD_DIR
 	string
@@ -25,22 +25,22 @@ config MAINBOARD_DIR
 
 config DCACHE_RAM_BASE
 	hex
-	default 0xc8000
+	default 0xc4000
 	depends on BOARD_TYAN_S2912_FAM10
 	
 config DCACHE_RAM_SIZE
 	hex
-	default 0x08000
+	default 0x0c000
 	depends on BOARD_TYAN_S2912_FAM10
 
 config DCACHE_RAM_GLOBAL_VAR_SIZE
 	hex
-	default 0x01000
+	default 0x04000
 	depends on BOARD_TYAN_S2912_FAM10
 
 config APIC_ID_OFFSET
 	hex	
-	default 16
+	default 0
 	depends on BOARD_TYAN_S2912_FAM10
 
 config MEM_TRAIN_SEQ
@@ -95,12 +95,12 @@ config HW_MEM_HOLE_SIZEK
 
 config MAX_CPUS
 	int
-	default 2
+	default 8
 	depends on BOARD_TYAN_S2912_FAM10
 
 config MAX_PHYSICAL_CPUS
 	int
-	default 1
+	default 2
 	depends on BOARD_TYAN_S2912_FAM10
 
 config HW_MEM_HOLE_SIZE_AUTO_INC
@@ -110,12 +110,12 @@ config HW_MEM_HOLE_SIZE_AUTO_INC
 
 config HT_CHAIN_UNITID_BASE
 	hex
-	default 0x0
+	default 0x1
 	depends on BOARD_TYAN_S2912_FAM10
 
 config HT_CHAIN_END_UNITID_BASE
 	hex	
-	default 0x0
+	default 0x20
 	depends on BOARD_TYAN_S2912_FAM10
 
 config USE_INIT
@@ -148,3 +148,27 @@ config AMD_UCODE_PATCH_FILE
 	default "mc_patch_01000095.h"
 	depends on BOARD_TYAN_S2912_FAM10
 
+config SERIAL_CPU_INIT
+	bool
+	default n
+	depends on BOARD_TYAN_S2912_FAM10
+
+config ACPI_SSDTX_NUM
+	hex
+	default 0x1f
+	depends on BOARD_TYAN_S2912_FAM10
+
+config RAMBASE
+	hex
+	default 0x200000
+	depends on BOARD_TYAN_S2912_FAM10
+
+config RAMTOP
+	hex
+	default 0x1000000
+	depends on BOARD_TYAN_S2912_FAM10
+
+config HEAP_SIZE
+	hex
+	default 0xc0000
+	depends on BOARD_TYAN_S2912_FAM10

src/mainboard/tyan/s2912_fam10/Makefile.inc

@@ -30,19 +30,12 @@ obj-$(CONFIG_AP_CODE_IN_CAR) += apc_auto.o
 
 # This is part of the conversion to init-obj and away from included code. 
 initobj-y += crt0.o
-crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
 crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
-crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
-crt0-y += ../../../../src/arch/i386/lib/id.inc
-crt0-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.inc
 crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
 crt0-y += auto.inc
 
 ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
-ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
+ldscript-y += ../../../../src/cpu/x86/32bit/entry32.lds
-ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
-ldscript-y += ../../../../src/arch/i386/lib/id.lds
-ldscript-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.lds
 ldscript-y += ../../../../src/arch/i386/lib/failover.lds
 ldscript-$(CONFIG_AP_CODE_IN_CAR) += ../../../../src/arch/i386/init/ldscript_apc.lb
 

src/southbridge/nvidia/mcp55/Makefile.inc

@@ -14,3 +14,6 @@ driver-y += mcp55_usb.o
 driver-$(CONFIG_GENERATE_ACPI_TABLES) += mcp55_fadt.o
 
 obj-y += mcp55_reset.o
+
+chipset_bootblock_inc += $(src)/southbridge/nvidia/mcp55/romstrap.inc
+chipset_bootblock_lds += $(src)/southbridge/nvidia/mcp55/romstrap.lds

src/southbridge/via/k8t890/Makefile.inc

@@ -7,3 +7,6 @@ driver-y += k8t890_pcie.o
 driver-y += k8t890_traf_ctrl.o
 driver-y += k8t890_error.o
 driver-y += k8m890_chrome.o
+
+chipset_bootblock_inc += $(src)/southbridge/via/k8t890/romstrap.inc
+chipset_bootblock_lds += $(src)/southbridge/via/k8t890/romstrap.lds