soc/amd/picasso/acpi: include pci_int_defs.asl from soc.asl

Instead of including pci_int_defs.asl in each board's DSDT, include it
in the common soc.asl. This moves the PRQM OperationRegion and the PRQI
IndexField defined in pci_int_defs.asl into the \_SB scope, but those
are defined inside the \_SB scope both in the Picasso reference code and
for the AMD SoCs from Cezanne on.

TEST=Both Linux and Windows still boot and don't show ACPI errors on
Mandolin after moving this inside the \_SB scope

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib4e7bfb15de184cc43cd17c8249be0f59405793f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>

src/mainboard/amd/bilby/dsdt.asl

@@ -16,9 +16,6 @@ DefinitionBlock (
 	#include <acpi/dsdt_top.asl>
 	#include <globalnvs.asl>
 
-	/* PCI IRQ mapping for the Southbridge */
-	#include <pci_int_defs.asl>
-
 	/* Power state notification to ALIB */
 	#include <pnot.asl>
 

src/mainboard/amd/mandolin/dsdt.asl

@@ -16,9 +16,6 @@ DefinitionBlock (
 	#include <acpi/dsdt_top.asl>
 	#include <globalnvs.asl>
 
-	/* PCI IRQ mapping for the Southbridge */
-	#include <pci_int_defs.asl>
-
 	/* Power state notification to ALIB */
 	#include <pnot.asl>
 

src/mainboard/google/zork/dsdt.asl

@@ -17,9 +17,6 @@ DefinitionBlock (
 	#include <acpi/dsdt_top.asl>
 	#include <globalnvs.asl>
 
-	/* PCI IRQ mapping for the Southbridge */
-	#include <pci_int_defs.asl>
-
 	/* Power state notification to ALIB */
 	#include <pnot.asl>
 

src/soc/amd/picasso/acpi/soc.asl

@@ -8,6 +8,9 @@ Device(PCI0) {
 	#include "sb_pci0_fch.asl"
 }
 
+/* PCI IRQ mapping for the Southbridge */
+#include "pci_int_defs.asl"
+
 /* Describe PCI INT[A-H] for the Southbridge */
 #include <soc/amd/common/acpi/pci_int.asl>