mb/google/nissa/var/pujjo: Enable PCIe port 3 for WWAN_5G

Pujjoteen5 support WWAN 5G device, enable PCIe port 3 for WWAN 5G device

BUG=b:281943398
TEST=Build and boot on pujjo

Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: I6d2e8eaecae968ed51095d9497beab492ba7e0c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>

src/mainboard/google/brya/Kconfig.name

@@ -277,6 +277,8 @@ config BOARD_GOOGLE_PUJJO
 	select DRIVERS_GENESYSLOGIC_GL9750
 	select DRIVERS_I2C_SX9324
 	select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER
+	select DRIVERS_WWAN_FM350GL
+	select HAVE_PCIE_WWAN
 	select HAVE_WWAN_POWER_SEQUENCE
 	select CHROMEOS_WIFI_SAR if CHROMEOS
 

src/mainboard/google/brya/variants/pujjo/fw_config.c

@@ -8,12 +8,20 @@
 static const struct pad_config lte_disable_pads[] = {
 	/* A8  : WWAN_RF_DISABLE_ODL */
 	PAD_NC(GPP_A8, NONE),
+	/* A12 : WWAN_PCIE_WAKE_ODL */
+	PAD_NC(GPP_A12, NONE),
+	/* D5  : SRCCLKREQ0# ==> WWAN_CLKREQ_ODL */
+	PAD_NC(GPP_D5, NONE),
 	/* D6  : WWAN_EN */
 	PAD_NC(GPP_D6, NONE),
+	/* D15  : EN_PP2800_WCAM_X ==> WWAN_SAR_DETECT_2_ODL */
+	PAD_NC(GPP_D15, NONE),
 	/* F12 : WWAN_RST_L */
 	PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG),
 	/* H19 : SOC_I2C_SUB_INT_ODL */
 	PAD_NC(GPP_H19, NONE),
+	/* H21  : WCAM_MCLK_R ==> WWAN_PERST_L */
+	PAD_NC_LOCK(GPP_H21, NONE, LOCK_CONFIG),
 	/* H23 : WWAN_SAR_DETECT_ODL */
 	PAD_NC(GPP_H23, NONE),
 };
@@ -36,7 +44,8 @@ static const struct pad_config stylus_disable_pads[] = {
 
 void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 {
-	if (!fw_config_probe(FW_CONFIG(LTE, LTE_PRESENT))) {
+	if (fw_config_probe(FW_CONFIG(LTE, LTE_ABSENT)) && fw_config_probe(FW_CONFIG(WWAN_5G, WWAN_5G_ABSENT))
+	) {
 		printk(BIOS_INFO, "Disable LTE-related GPIO pins.\n");
 		gpio_padbased_override(padbased_table, lte_disable_pads,
 						ARRAY_SIZE(lte_disable_pads));

src/mainboard/google/brya/variants/pujjo/include/variant/gpio.h

@@ -7,6 +7,8 @@
 
 #define WWAN_FCPO	GPP_D6
 #define WWAN_RST	GPP_F12
+#define WWAN_PERST      GPP_H21
+#define T1_OFF_MS	20
 #define T2_OFF_MS	20
 
 #endif

src/mainboard/google/brya/variants/pujjo/overridetree.cb

@@ -35,6 +35,10 @@ fw_config
 		option WIFI_SAR_TABLE_1		1
 		option WIFI_SAR_TABLE_2		2
 	end
+	field WWAN_5G 19
+		option WWAN_5G_ABSENT		0
+		option WWAN_5G_PRESENT		1
+	end
 
 end
 
@@ -526,6 +530,36 @@ chip soc/intel/alderlake
 				end
 			end
 		end
+		device ref pcie_rp3 on
+			# WWAN PCIE 3 using clk 0
+			register "pch_pcie_rp[PCH_RP(3)]" = "{
+				.clk_src = 0,
+				.clk_req = 0,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H21)"
+				register "reset_off_delay_ms" = "20"
+				register "srcclk_pin" = "0"
+				register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL"
+				register "skip_on_off_support" = "true"
+				device generic 0 alias rp3_rtd3 on
+				    probe WWAN_5G WWAN_5G_PRESENT
+				end
+			end
+			chip drivers/wwan/fm
+				register "fcpo_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D6)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F12)"
+				register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H21)"
+				register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A12)"
+				register "add_acpi_dma_property" = "true"
+				use rp3_rtd3 as rtd3dev
+				device generic 0 on
+				    probe WWAN_5G WWAN_5G_PRESENT
+				end
+			end
+			probe WWAN_5G WWAN_5G_PRESENT
+		end
 		device ref pcie_rp4 on
 			# PCIe 4 WLAN
 			register "pch_pcie_rp[PCH_RP(4)]" = "{