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soc/intel/mtl: Call cse_fill_bp_info early in romstage 

Intel Platform Service Record(PSR) will be enabled on Meteor Lake
platforms. cse_fw_sync actions happen in ramstage when PSR is enabled.
To avoid the boot time penalty of sending the cse_get_bp_info in
ramstage, call cse_fill_bp_info to get cse_bp_info response early in
romstage and store in cbmem. This data can be later used in ramstage.

BUG=b:273207144
TEST=Verify cse_bp_info is filled in romstage in rex.

Change-Id: Ic0e8fb34f21ff07e182a7b848d38e9d329010028
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit is contained in:
Krishna Prasad Bhat 2023-09-22 00:38:53 +05:30 committed by Subrata Banik
parent 4f062ec34b
commit 7542fa19a9
1 changed files with 5 additions and 2 deletions
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7
src/soc/intel/meteorlake/romstage/romstage.c
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@ -129,8 +129,11 @@ void mainboard_romstage_entry(void)
/* Initialize HECI interface */
cse_init(HECI1_BASE_ADDRESS);
if (!s3wake && CONFIG(SOC_INTEL_CSE_LITE_SKU))
cse_fw_sync();
if (!s3wake && CONFIG(SOC_INTEL_CSE_LITE_SKU)) {
cse_fill_bp_info();
if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE))
cse_fw_sync();
}
/* Update coreboot timestamp table with CSE timestamps */
if (CONFIG(SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY))