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Rewrite i82801dbm_enable to do nothing if device does not have an enable/disable bit. 

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2041 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Steven J. Magnani 2005-09-21 13:49:44 +00:00
parent e355b2ac60
commit 7557331605
1 changed files with 47 additions and 38 deletions
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85
src/southbridge/intel/i82801dbm/i82801dbm.c
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@ -6,48 +6,57 @@
void i82801dbm_enable(device_t dev)
{
device_t lpc_dev;
unsigned int index;
uint16_t reg_old, reg;
unsigned int index = 0;
uint8_t bHasDisableBit = 0;
uint16_t cur_disable_mask, new_disable_mask;
// all 82801dbm device ares in bus 0
unsigned int devfn;
devfn = PCI_DEVFN(0x1f, 0); // lpc
lpc_dev = dev_find_slot(0, devfn); // 0
if (!lpc_dev ) {
// all 82801dbm devices are in bus 0
unsigned int devfn = PCI_DEVFN(0x1f, 0); // lpc
device_t lpc_dev = dev_find_slot(0, devfn); // 0
if (!lpc_dev)
return;
}
#if 0
if ((lpc_dev->vendor != PCI_VENDOR_ID_INTEL) ||
(lpc_dev->device != PCI_DEVICE_ID_INTEL_82801DBM_1F0)) {
uint32_t id;
id = pci_read_config32(lpc_dev, PCI_VENDOR_ID);
if (id != (PCI_VENDOR_ID_INTEL | (PCI_DEVICE_ID_INTEL_82801DBM_1F0 << 16))) {
return;
// Calculate disable bit position for specified device:function
// NOTE: For ICH-4, only the following devices can be disabled:
// D31: F0, F1, F3, F5, F6,
// D29: F0, F1, F2, F7
if (PCI_SLOT(dev->path.u.pci.devfn) == 31) {
index = PCI_FUNC(dev->path.u.pci.devfn);
switch (index) {
case 0:
case 1:
case 3:
case 5:
case 6:
bHasDisableBit = 1;
break;
default:
break;
};
if (index == 0)
index = 14; // D31:F0 bit is an exception
} else if (PCI_SLOT(dev->path.u.pci.devfn) == 29) {
index = 8 + PCI_FUNC(dev->path.u.pci.devfn);
if ((PCI_FUNC(dev->path.u.pci.devfn) < 3) || (PCI_FUNC(dev->path.u.pci.devfn) == 7))
bHasDisableBit = 1;
}
if (bHasDisableBit) {
cur_disable_mask = pci_read_config16(lpc_dev, FUNC_DIS);
new_disable_mask = cur_disable_mask & ~(1<<index); // enable it
if (!dev->enabled) {
new_disable_mask |= (1<<index); // disable it
}
if (new_disable_mask != cur_disable_mask) {
pci_write_config16(lpc_dev, FUNC_DIS, new_disable_mask);
}
}
#endif
index = (dev->path.u.pci.devfn & 7);
if((dev->path.u.pci.devfn & ~0x7)==devfn) { // D=0x1f
if(index==0){ //1f0
index = 14;
}
} else { // D=0x1d
index += 8;
}
reg_old = pci_read_config16(lpc_dev, FUNC_DIS);
reg = reg_old;
reg &= ~(1<<index); // enable it
if (!dev->enabled) {
reg |= (1<<index); // disable it
}
if (reg != reg_old) {
pci_write_config16(lpc_dev, FUNC_DIS, reg);
}
reg = pci_read_config16(lpc_dev, FUNC_DIS);
}
struct chip_operations southbridge_intel_i82801dbm_control = {