mainboard/bap: Add support for BAP ODE E20XX
Adding new board based on AMD Kabini. Most of the code is copied from gizmosphere/gizmo2 Board is developed by BAP - Bruhnspace Advanced Projects: http://www.unibap.com/ (Site is under construction) Special on this board is: -Soldered down memory -SuperIO Fintek F81866D Known bugs: -S3 doesnt work -Serial ports only works for the first boot. Needs power cut. Tested with: -SeaBios as Payload -Linux OS - Lubuntu 14.10 32/64Bit, Kernel 3.19 - 4.1 -Windows 8 64Bit Change-Id: I7e2b306620dd152a9f01ab6ccf2a0a880a068adb Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com> Reviewed-on: http://review.coreboot.org/10288 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Fabian Kunkel
Patrick Georgi
parent
2a38551bb7
commit
7558dbac31
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@ -1,3 +1,22 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2015 BAP - Bruhnspace Advanced Projects
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## (Written by Fabian Kunkel <fabi@adv.bruhnspace.com> for BAP)
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc.
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##
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if VENDOR_BAP
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choice
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@ -2,6 +2,8 @@
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2014 Sage Electronic Engineering, LLC.
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# Copyright (C) 2015 BAP - Bruhnspace Advanced Projects
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# (Written by Fabian Kunkel <fabi@adv.bruhnspace.com> for BAP)
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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@ -16,21 +18,17 @@
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# along with this program; if not, write to the Free Software
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# Foundation, Inc.
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# Gizmo2 has 1GB using 4 Micron_MT41J128M16JT-125 chips
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# The datasheet is available at:
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# http://download.micron.com/pdf/datasheets/dram/ddr3/2Gb_DDR3_SDRAM.pdf
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# SPD contents for Gizmo2 2GB DDR3 (1600MHz PC3-12800) soldered down
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# BAP ODE E20XX has 2GB ram soldered down on the Q7
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# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
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# bits[3:0]: 1 = 128 SPD Bytes Used
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# bits[6:4]: 1 = 256 SPD Bytes Total
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# bit7 : 0 = CRC covers bytes 0 ~ 125
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11
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92
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# 1 SPD Revision -
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# 0x10 = Revision 1.0
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10
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12
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# 2 Key Byte / DRAM Device Type
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# bits[7:0]: 0x0b = DDR3 SDRAM
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@ -45,13 +43,13 @@
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# bits[3:0]: 3 = 2 Gigabits Total SDRAM capacity per chip
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# bits[6:4]: 0 = 3 (8 banks)
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# bit7 : reserved
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03
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04
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# 5 SDRAM Addressing
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# bits[2:0]: 1 = 10 Column Address Bits
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# bits[5:3]: 2 = 14 Row Address Bits
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# bits[7:6]: reserved
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11
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19
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# 6 Module Nominal Voltage, VDD
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# bit0 : 0 = 1.5 V operable
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@ -70,7 +68,7 @@
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# bits[2:0]: 3 = Primary bus width is 64 bits
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# bits[4:3]: 0 = 0 bits (no bus width extension)
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# bits[7:5]: reserved
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03
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08
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# 9 Fine Timebase (FTB) Dividend / Divisor
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# bits[3:0]: 0x02 divisor
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@ -85,7 +83,7 @@
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# 12 SDRAM Minimum Cycle Time (tCKmin)
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# 0x0a = tCKmin of 1.25 ns = DDR3-1600 (800 MHz clock)
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0A
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0C
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# 13 Reserved
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00
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@ -93,11 +91,11 @@
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# 14 CAS Latencies Supported, Least Significant Byte
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# 15 CAS Latencies Supported, Most Significant Byte
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# Cas Latencies of 11 - 5 are supported
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FE 00
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7E 00
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# 16 Minimum CAS Latency Time (tAAmin)
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# 0x6E = 13.75ns - DDR3-1600K
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6E
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69
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# 17 Minimum Write Recovery Time (tWRmin)
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# 0x78 = tWR of 15ns - All DDR3 speed grades
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@ -105,7 +103,7 @@ FE 00
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# 18 Minimum RAS# to CAS# Delay Time (tRCDmin)
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# 0x6E = 13.75ns - DDR3-1600K
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6E
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69
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# 19 Minimum Row Active to Row Active Delay Time (tRRDmin)
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# 0x3C = 7.5ns
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@ -113,7 +111,7 @@ FE 00
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# 20 Minimum Row Precharge Delay Time (tRPmin)
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# 0x6E = 13.75ns - DDR3-1600K
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6E
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69
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# 21 Upper Nibbles for tRAS and tRC
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# bits[3:0]: tRAS most significant nibble = 1 (see byte 22)
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@ -122,16 +120,16 @@ FE 00
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# 22 Minimum Active to Precharge Delay Time (tRASmin), LSB
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# 0x118 = 35ns - DDR3-1600 (see byte 21)
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18
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20
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# 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB
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# 0x186 = 48.75ns - DDR3-1600K
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86
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89
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# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB
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# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB
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# 0x500 = 160ns - for 2 Gigabit chips
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00 05
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20 08
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# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin)
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# 0x3c = 7.5 ns - All DDR3 SDRAM speed bins
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@ -144,7 +142,7 @@ FE 00
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# 28 Upper Nibble for tFAWmin
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# 29 Minimum Four Activate Window Delay Time (tFAWmin)
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# 0x0140 = 40ns - DDR3-1600, 2 KB page size
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01 40
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01 68
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# 30 SDRAM Optional Feature
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# bit0 : 1= RZQ/6 supported
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@ -160,7 +158,7 @@ FE 00
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# bit3 : 0 = no on die thermal sensor
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# bits[6:4]: reserved
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# bit7 : 0 = partial self refresh supported
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05
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01
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# 32 Module Thermal Sensor
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# 0 = Thermal sensor not incorporated onto this assembly
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@ -188,18 +186,18 @@ FE 00
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# 60 Raw Card Extension, Module Nominal Height
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# bits[4:0]: 0 = <= 15mm tall
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# bits[7:5]: 0 = raw card revision 0-3
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00
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0f
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# 61 Module Maximum Thickness
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# bits[3:0]: 0 = thickness front <= 1mm
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# bits[7:4]: 0 = thinkness back <= 1mm
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00
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11
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# 62 Reference Raw Card Used
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# bits[4:0]: 0 = Reference Raw card A used
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# bits[6:5]: 0 = revision 0
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# bit7 : 0 = Reference raw cards A through AL
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00
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22
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# 63 Address Mapping from Edge Connector to DRAM
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# bit0 : 0 = standard mapping (not mirrored)
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@ -217,19 +215,68 @@ FE 00
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# 117 - 118 Module ID: Module Manufacturers JEDEC ID Code
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# 0x0001 = AMD
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00 01
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80 AD
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# 119 Module ID: Module Manufacturing Location - oem specified
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# 120 Module ID: Module Manufacture Year in BCD
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# 0x13 = 2013
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00 13
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01 00
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# 121 Module ID: Module Manufacture week
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# 0x12 = 12th week
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12
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00
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# 122 - 125: Module Serial Number
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53 41 47 45
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00 00 00 00
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# 126 - 127: Cyclical Redundancy Code
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00 00
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D4 51
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# Coreboot is only interested in the first 128 values
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#128 - 135
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48 4d 54 34 32 35 53 36
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#136 - 143
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4d 46 52 36 43 2d 48 39
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#144 - 151
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20 20 4e 30 80 ad 00 00
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#152 - 159
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00 00 00 00 00 00 00 00
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#160 - 167
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00 00 00 00 00 00 00 00
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#168 - 175
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00 00 00 00 00 00 00 00
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#176 - 183
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00 00 00 00 00 00 00 00
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#184 - 191
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00 00 00 00 00 00 00 00
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#192 - 199
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00 00 00 00 00 00 00 00
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#200 - 207
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00 00 00 00 00 00 00 00
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#208 - 215
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00 00 00 00 00 00 00 00
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#216 - 223
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00 00 00 00 00 00 00 00
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#224 - 231
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00 00 00 00 00 00 00 00
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#232 - 239
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00 00 00 00 00 00 00 00
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#240 - 247
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00 00 00 00 00 00 00 00
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#248 - 255
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00 00 00 00 00 00 00 00
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@ -31,6 +31,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select HAVE_ACPI_TABLES
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select BOARD_ROMSIZE_KB_4096
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select GFXUMA
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select SUPERIO_FINTEK_F81866D
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select SPD_CACHE
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config MAINBOARD_DIR
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@ -30,7 +30,7 @@ ramstage-y += PlatformGnbPcie.c
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SPD_BIN = $(obj)/spd.bin
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# Order of names in SPD_SOURCES is important!
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SPD_SOURCES = Micron_MT41J128M16JT
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SPD_SOURCES = BAP_Q7
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SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
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@ -32,7 +32,7 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
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0,
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PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3),
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PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 5,
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HotplugDisabled,
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HotplugBasic,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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AspmDisabled, 0x01, 0)
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@ -42,7 +42,7 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
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0,
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PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 2),
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PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4,
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HotplugDisabled,
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HotplugBasic,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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AspmDisabled, 0x02, 0)
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@ -72,7 +72,7 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
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DESCRIPTOR_TERMINATE_LIST,
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PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7),
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PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1,
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HotplugDisabled,
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HotplugBasic,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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AspmDisabled, 0x05, 0)
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@ -80,17 +80,17 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
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};
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static const PCIe_DDI_DESCRIPTOR DdiList [] = {
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/* DP0 to HDMI0/DP */
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/* eDP0 to LVDS connector*/
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11),
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PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux1, Hdp1)
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PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1)
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},
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/* DP1 to high-speed edge connector */
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/* DP1 to HDMI */
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{
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DESCRIPTOR_TERMINATE_LIST,
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PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15),
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PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2)
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PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2)
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},
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};
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@ -2,6 +2,8 @@
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Sage Electronic Engineering, LLC
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* Copyright (C) 2015 BAP - Bruhnspace Advanced Projects
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* (Written by Fabian Kunkel <fabi@adv.bruhnspace.com> for BAP)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -17,4 +19,34 @@
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* Foundation, Inc.
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*/
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/* No Super I/O device or functionality yet */
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/* SuperIO support for Windows */
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Device (UAR1) {
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Name (_HID, EISAID ("PNP0501"))
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Name (_UID, 1)
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Name (_CRS, ResourceTemplate ()
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{
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IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08)
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IRQNoFlags () {4}
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})
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Name (_PRS, ResourceTemplate ()
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{
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IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08)
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IRQNoFlags () {4}
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})
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}
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Device (UAR2) {
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Name (_HID, EISAID ("PNP0501"))
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Name (_UID, 2)
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Name (_CRS, ResourceTemplate ()
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{
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IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08)
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IRQNoFlags () {3}
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})
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Name (_PRS, ResourceTemplate ()
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{
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IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08)
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IRQNoFlags () {3}
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})
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}
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@ -9,7 +9,7 @@
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
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#
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# You should have received a copy of the GNU General Public License
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@ -32,11 +32,11 @@ chip northbridge/amd/agesa/family16kb/root_complex
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device pci 1.0 on end # Internal Graphics P2P bridge 0x9835
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device pci 1.1 on end # Internal Multimedia
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device pci 2.0 on end # PCIe Host Bridge
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device pci 2.1 on end # PCIe GFX Bridge
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device pci 2.2 on end # PCIe GPP mini PCIe
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device pci 2.3 on end # PCIe LAN
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device pci 2.4 on end # PCIe x2 to high speed edge connector
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device pci 2.5 on end # PCIe x2 to high speed edge connector
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device pci 2.1 on end # x4 PCIe Slot
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device pci 2.2 on end # PCIe Q7 Realtek GBit LAN
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device pci 2.3 on end # PCIe CB Realtek GBit LAN
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device pci 2.4 on end # PCIe BAP FPGA
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device pci 2.5 on end # PCIe BAP FPGA (unused, for 050T)
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end #chip northbridge/amd/agesa/family16kb
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chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus
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@ -48,7 +48,60 @@ chip northbridge/amd/agesa/family16kb/root_complex
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device pci 13.2 on end # USB
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device pci 14.0 on end # SM
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device pci 14.2 on end # HDA 0x4383
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device pci 14.3 on end # LPC 0x439d
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device pci 14.3 on # LPC 0x439d
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chip superio/fintek/f81866d
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register "hwm_amd_tsi_addr" = "0x98" # Set to AMD
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register "hwm_amd_tsi_control" = "0x02" # Set to AMD
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register "hwm_fan_select" = "0xC0" # Sets Fan2 to PWM
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register "hwm_fan_mode" = "0xD5" # Sets FAN1-3 to Auto RPM mode
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register "hwm_fan3_control" = "0x00" # Fan control 23kHz
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register "hwm_fan2_temp_map_select" = "0x1E" # Fan control 23kHz
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register "hwm_fan2_bound1" = "0x3C" # 60°C
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register "hwm_fan2_bound2" = "0x32" # 50°C
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register "hwm_fan2_bound3" = "0x28" # 40°C
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register "hwm_fan2_bound4" = "0x1E" # 30°C
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register "hwm_fan2_seg1_speed" = "0xFF" # 100%
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register "hwm_fan2_seg2_speed" = "0xD9" # 85%
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register "hwm_fan2_seg3_speed" = "0xB2" # 70%
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register "hwm_fan2_seg4_speed" = "0x99" # 60%
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register "hwm_fan2_seg5_speed" = "0x80" # 50%
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register "hwm_temp_sens_type" = "0x04" # Sets temp sensor 1 type to to thermistor
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device pnp 4e.0 off # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 4e.3 off end # Parallel Port
|
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device pnp 4e.4 on # Hardware Monitor
|
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io 0x60 = 0x295
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irq 0x70 = 0
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end
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device pnp 4e.5 off # Keyboard
|
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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end
|
||||
device pnp 4e.6 off end # GPIO
|
||||
device pnp 4e.7 on end # WDT
|
||||
device pnp 4e.a off end # PME
|
||||
device pnp 4e.10 on # COM1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 4e.11 on # COM2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 4e.12 off # COM3
|
||||
end
|
||||
device pnp 4e.13 off # COM4
|
||||
end
|
||||
device pnp 4e.14 off # COM5
|
||||
end
|
||||
device pnp 4e.15 off # COM6
|
||||
end
|
||||
end # f81866d
|
||||
end #LPC
|
||||
device pci 14.7 on end # SD
|
||||
end #chip southbridge/amd/hudson
|
||||
|
||||
|
|
|
|||
|
|
@ -2,6 +2,8 @@
|
|||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2012 Advanced Micro Devices, Inc.
|
||||
* Copyright (C) 2015 BAP - Bruhnspace Advanced Projects
|
||||
* (Written by Fabian Kunkel <fabi@adv.bruhnspace.com> for BAP)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
|
|
@ -35,21 +37,16 @@
|
|||
#include <cpu/x86/lapic.h>
|
||||
#include <southbridge/amd/agesa/hudson/hudson.h>
|
||||
#include <cpu/amd/agesa/s3_resume.h>
|
||||
#include <superio/fintek/common/fintek.h>
|
||||
#include <superio/fintek/f81866d/f81866d.h>
|
||||
#include "cbmem.h"
|
||||
|
||||
#define SERIAL_DEV1 PNP_DEV(0x4e, F81866D_SP1)
|
||||
|
||||
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
/* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
|
||||
* LpcClk[1:0]". To be consistent with Parmer, setting to 4mA
|
||||
* even though the register is not documented in the Kabini BKDG.
|
||||
* Otherwise the serial output is bad code.
|
||||
*/
|
||||
outb(0xD2, 0xcd6);
|
||||
outb(0x00, 0xcd7);
|
||||
|
||||
amd_initmmio();
|
||||
|
||||
/* Set LPC decode enables. */
|
||||
|
|
@ -62,6 +59,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
|||
post_code(0x30);
|
||||
|
||||
post_code(0x31);
|
||||
fintek_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE);
|
||||
console_init();
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue