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This patch moves one of the CAR configs to the socket from the single 

mainboard that uses it.

Signed-off-by: Warren Turkal <wt@penguintechs.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5868 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Warren Turkal 2010-09-27 21:11:54 +00:00 committed by Stefan Reinauer
parent 7cdf1eca92
commit 7571c0b566
2 changed files with 16 additions and 9 deletions
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16
src/cpu/intel/socket_441/Kconfig
View File

@ -1,5 +1,21 @@
config CPU_INTEL_SOCKET_441 config CPU_INTEL_SOCKET_441
bool bool
if CPU_INTEL_SOCKET_441
config SOCKET_SPECIFIC_OPTIONS # dummy
def_bool y
select CPU_INTEL_MODEL_106CX select CPU_INTEL_MODEL_106CX
select MMX select MMX
select SSE select SSE
select CACHE_AS_RAM
config DCACHE_RAM_BASE
hex
default 0xffdf8000
config DCACHE_RAM_SIZE
hex
default 0x8000
endif # CPU_INTEL_SOCKET_441

9
src/mainboard/intel/d945gclf/Kconfig
View File

@ -38,7 +38,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_ACPI_TABLES select HAVE_ACPI_TABLES
select HAVE_SMI_HANDLER select HAVE_SMI_HANDLER
select BOARD_ROMSIZE_KB_512 select BOARD_ROMSIZE_KB_512
select CACHE_AS_RAM
select GFXUMA select GFXUMA
select TINY_BOOTBLOCK select TINY_BOOTBLOCK
@ -46,14 +45,6 @@ config MAINBOARD_DIR
string string
default intel/d945gclf default intel/d945gclf
config DCACHE_RAM_BASE
hex
default 0xffdf8000
config DCACHE_RAM_SIZE
hex
default 0x8000
config MAINBOARD_PART_NUMBER config MAINBOARD_PART_NUMBER
string string
default "D945GCLF" default "D945GCLF"