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soc: Remove SOC_SPECIFIC_OPTIONS 

Move specific options under the boolean and remove dummy
SOC_SPECIFIC_OPTIONS.

Change-Id: I6ae52ceb61489e5a050a60d1fbbf4250960407eb
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
This commit is contained in:
Elyes Haouas 2023-08-21 20:39:25 +02:00 committed by Martin L Roth
parent a1957314c2
commit 757509113b
7 changed files with 94 additions and 115 deletions
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11
src/soc/example/min86/Kconfig
View File

@ -1,5 +1,9 @@
config SOC_EXAMPLE_MIN86
bool
select ARCH_X86
select NO_MONOTONIC_TIMER
select NO_ECAM_MMCONF_SUPPORT
select UNKNOWN_TSC_RATE
help
This example SoC code along with the example/min86 mainboard
should serve as a minimal example how a buildable x86 SoC code
@ -12,13 +16,6 @@ config SOC_EXAMPLE_MIN86
if SOC_EXAMPLE_MIN86
config SOC_SPECIFIC_OPTIONS
def_bool y
select ARCH_X86
select NO_MONOTONIC_TIMER
select NO_ECAM_MMCONF_SUPPORT
select UNKNOWN_TSC_RATE
config DCACHE_BSP_STACK_SIZE # required by arch/x86/car.ld
default 0x100

39
src/soc/intel/apollolake/Kconfig
View File

@ -1,27 +1,6 @@
config SOC_INTEL_APOLLOLAKE
bool
select INTEL_CAR_CQOS
help
Intel Apollolake support
config SOC_INTEL_GEMINILAKE
bool
default n
select SOC_INTEL_APOLLOLAKE
select SOC_INTEL_COMMON_BLOCK_CNVI
select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
select SOC_INTEL_COMMON_BLOCK_SGX
select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
select IDT_IN_EVERY_STAGE
select PAGING_IN_CACHE_AS_RAM
select INTEL_CAR_NEM
help
Intel Geminilake support
if SOC_INTEL_APOLLOLAKE
config CPU_SPECIFIC_OPTIONS
def_bool y
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select ACPI_NO_PCAT_8259
select ARCH_X86
@ -102,6 +81,24 @@ config CPU_SPECIFIC_OPTIONS
# This SoC does not map SPI flash like many previous SoC. Therefore we
# provide a custom media driver that facilitates mapping
select X86_CUSTOM_BOOTMEDIA
help
Intel Apollolake support
config SOC_INTEL_GEMINILAKE
bool
default n
select SOC_INTEL_APOLLOLAKE
select SOC_INTEL_COMMON_BLOCK_CNVI
select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
select SOC_INTEL_COMMON_BLOCK_SGX
select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
select IDT_IN_EVERY_STAGE
select PAGING_IN_CACHE_AS_RAM
select INTEL_CAR_NEM
help
Intel Geminilake support
if SOC_INTEL_APOLLOLAKE
config SKIP_CSE_RBP
bool

11
src/soc/intel/baytrail/Kconfig
View File

@ -1,12 +1,5 @@
config SOC_INTEL_BAYTRAIL
bool
help
Bay Trail M/D part support.
if SOC_INTEL_BAYTRAIL
config CPU_SPECIFIC_OPTIONS
def_bool y
select ACPI_COMMON_MADT_IOAPIC
select ACPI_COMMON_MADT_LAPIC
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
@ -38,6 +31,10 @@ config CPU_SPECIFIC_OPTIONS
select CPU_HAS_L2_ENABLE_MSR
select TCO_SPACE_NOT_YET_SPLIT
select USE_DDR3
help
Bay Trail M/D part support.
if SOC_INTEL_BAYTRAIL
config VBOOT
select VBOOT_MUST_REQUEST_DISPLAY

11
src/soc/intel/braswell/Kconfig
View File

@ -1,12 +1,5 @@
config SOC_INTEL_BRASWELL
bool
help
Braswell M/D part support.
if SOC_INTEL_BRASWELL
config CPU_SPECIFIC_OPTIONS
def_bool y
select ACPI_COMMON_MADT_IOAPIC
select ACPI_COMMON_MADT_LAPIC
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
@ -44,6 +37,10 @@ config CPU_SPECIFIC_OPTIONS
select SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT
select NO_CBFS_MCACHE
select TCO_SPACE_NOT_YET_SPLIT
help
Braswell M/D part support.
if SOC_INTEL_BRASWELL
config DCACHE_BSP_STACK_SIZE
hex

107
src/soc/intel/cannonlake/Kconfig
View File

@ -1,60 +1,5 @@
config SOC_INTEL_CANNONLAKE_BASE
bool
config SOC_INTEL_COFFEELAKE
bool
select SOC_INTEL_CANNONLAKE_BASE
select FSP_USES_CB_STACK
select HAVE_EXP_X86_64_SUPPORT
select HAVE_INTEL_FSP_REPO
select HECI_DISABLE_USING_SMM
select INTEL_CAR_NEM
select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
config SOC_INTEL_WHISKEYLAKE
bool
select SOC_INTEL_CANNONLAKE_BASE
select FSP_USES_CB_STACK
select HAVE_INTEL_FSP_REPO
select HECI_DISABLE_USING_SMM
select INTEL_CAR_NEM_ENHANCED
select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
config SOC_INTEL_COMETLAKE
bool
select SOC_INTEL_CANNONLAKE_BASE
select FSP_USES_CB_STACK
select HAVE_INTEL_FSP_REPO
select INTEL_CAR_NEM_ENHANCED
select PMC_IPC_ACPI_INTERFACE if DISABLE_HECI1_AT_PRE_BOOT
select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC
select SOC_INTEL_COMMON_BASECODE
select SOC_INTEL_COMMON_BASECODE_RAMTOP
config SOC_INTEL_COMETLAKE_1
bool
select SOC_INTEL_COMETLAKE
config SOC_INTEL_COMETLAKE_2
bool
select SOC_INTEL_COMETLAKE
config SOC_INTEL_COMETLAKE_S
bool
select SOC_INTEL_COMETLAKE
config SOC_INTEL_COMETLAKE_V
bool
select SOC_INTEL_COMETLAKE
config SOC_INTEL_CANNONLAKE_PCH_H
bool
if SOC_INTEL_CANNONLAKE_BASE
config CPU_SPECIFIC_OPTIONS
def_bool y
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select ACPI_NHLT
select ARCH_X86
@ -124,6 +69,58 @@ config CPU_SPECIFIC_OPTIONS
select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
select X86_CLFLUSH_CAR
config SOC_INTEL_COFFEELAKE
bool
select SOC_INTEL_CANNONLAKE_BASE
select FSP_USES_CB_STACK
select HAVE_EXP_X86_64_SUPPORT
select HAVE_INTEL_FSP_REPO
select HECI_DISABLE_USING_SMM
select INTEL_CAR_NEM
select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
config SOC_INTEL_WHISKEYLAKE
bool
select SOC_INTEL_CANNONLAKE_BASE
select FSP_USES_CB_STACK
select HAVE_INTEL_FSP_REPO
select HECI_DISABLE_USING_SMM
select INTEL_CAR_NEM_ENHANCED
select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
config SOC_INTEL_COMETLAKE
bool
select SOC_INTEL_CANNONLAKE_BASE
select FSP_USES_CB_STACK
select HAVE_INTEL_FSP_REPO
select INTEL_CAR_NEM_ENHANCED
select PMC_IPC_ACPI_INTERFACE if DISABLE_HECI1_AT_PRE_BOOT
select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC
select SOC_INTEL_COMMON_BASECODE
select SOC_INTEL_COMMON_BASECODE_RAMTOP
config SOC_INTEL_COMETLAKE_1
bool
select SOC_INTEL_COMETLAKE
config SOC_INTEL_COMETLAKE_2
bool
select SOC_INTEL_COMETLAKE
config SOC_INTEL_COMETLAKE_S
bool
select SOC_INTEL_COMETLAKE
config SOC_INTEL_COMETLAKE_V
bool
select SOC_INTEL_COMETLAKE
config SOC_INTEL_CANNONLAKE_PCH_H
bool
if SOC_INTEL_CANNONLAKE_BASE
config MAX_CPUS
int
default 20 if SOC_INTEL_CANNONLAKE_PCH_H && SOC_INTEL_COMETLAKE

19
src/soc/intel/denverton_ns/Kconfig
View File

@ -2,17 +2,6 @@
config SOC_INTEL_DENVERTON_NS
bool
help
Intel Denverton-NS SoC support
if SOC_INTEL_DENVERTON_NS
config CPU_INTEL_NUM_FIT_ENTRIES
int
default 1
config CPU_SPECIFIC_OPTIONS
def_bool y
select ARCH_X86
select BOOT_DEVICE_SUPPORTS_WRITES
select CACHE_MRC_SETTINGS
@ -50,6 +39,14 @@ config CPU_SPECIFIC_OPTIONS
select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
help
Intel Denverton-NS SoC support
if SOC_INTEL_DENVERTON_NS
config CPU_INTEL_NUM_FIT_ENTRIES
int
default 1
config ECAM_MMCONF_BASE_ADDRESS
default 0xe0000000

11
src/soc/intel/elkhartlake/Kconfig
View File

@ -1,12 +1,5 @@
config SOC_INTEL_ELKHARTLAKE
bool
help
Intel Elkhartlake support
if SOC_INTEL_ELKHARTLAKE
config CPU_SPECIFIC_OPTIONS
def_bool y
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select ARCH_X86
select BOOT_DEVICE_SUPPORTS_WRITES
@ -69,6 +62,10 @@ config CPU_SPECIFIC_OPTIONS
select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
select SOC_INTEL_RAPL_DISABLE_VIA_MCHBAR
select X86_CLFLUSH_CAR
help
Intel Elkhartlake support
if SOC_INTEL_ELKHARTLAKE
config MAX_CPUS
int