soc: Remove SOC_SPECIFIC_OPTIONS
Move specific options under the boolean and remove dummy SOC_SPECIFIC_OPTIONS. Change-Id: I6ae52ceb61489e5a050a60d1fbbf4250960407eb Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
This commit is contained in:
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a1957314c2
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@ -1,5 +1,9 @@
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config SOC_EXAMPLE_MIN86
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config SOC_EXAMPLE_MIN86
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bool
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bool
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select ARCH_X86
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select NO_MONOTONIC_TIMER
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select NO_ECAM_MMCONF_SUPPORT
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select UNKNOWN_TSC_RATE
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help
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help
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This example SoC code along with the example/min86 mainboard
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This example SoC code along with the example/min86 mainboard
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should serve as a minimal example how a buildable x86 SoC code
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should serve as a minimal example how a buildable x86 SoC code
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@ -12,13 +16,6 @@ config SOC_EXAMPLE_MIN86
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if SOC_EXAMPLE_MIN86
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if SOC_EXAMPLE_MIN86
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config SOC_SPECIFIC_OPTIONS
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def_bool y
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select ARCH_X86
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select NO_MONOTONIC_TIMER
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select NO_ECAM_MMCONF_SUPPORT
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select UNKNOWN_TSC_RATE
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config DCACHE_BSP_STACK_SIZE # required by arch/x86/car.ld
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config DCACHE_BSP_STACK_SIZE # required by arch/x86/car.ld
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default 0x100
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default 0x100
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@ -1,27 +1,6 @@
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config SOC_INTEL_APOLLOLAKE
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config SOC_INTEL_APOLLOLAKE
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bool
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bool
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select INTEL_CAR_CQOS
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select INTEL_CAR_CQOS
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help
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Intel Apollolake support
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config SOC_INTEL_GEMINILAKE
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bool
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default n
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select SOC_INTEL_APOLLOLAKE
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select SOC_INTEL_COMMON_BLOCK_CNVI
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select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
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select SOC_INTEL_COMMON_BLOCK_SGX
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select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
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select IDT_IN_EVERY_STAGE
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select PAGING_IN_CACHE_AS_RAM
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select INTEL_CAR_NEM
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help
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Intel Geminilake support
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if SOC_INTEL_APOLLOLAKE
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config CPU_SPECIFIC_OPTIONS
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def_bool y
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select ACPI_INTEL_HARDWARE_SLEEP_VALUES
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select ACPI_INTEL_HARDWARE_SLEEP_VALUES
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select ACPI_NO_PCAT_8259
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select ACPI_NO_PCAT_8259
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select ARCH_X86
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select ARCH_X86
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@ -102,6 +81,24 @@ config CPU_SPECIFIC_OPTIONS
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# This SoC does not map SPI flash like many previous SoC. Therefore we
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# This SoC does not map SPI flash like many previous SoC. Therefore we
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# provide a custom media driver that facilitates mapping
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# provide a custom media driver that facilitates mapping
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select X86_CUSTOM_BOOTMEDIA
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select X86_CUSTOM_BOOTMEDIA
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help
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Intel Apollolake support
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config SOC_INTEL_GEMINILAKE
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bool
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default n
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select SOC_INTEL_APOLLOLAKE
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select SOC_INTEL_COMMON_BLOCK_CNVI
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select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
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select SOC_INTEL_COMMON_BLOCK_SGX
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select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
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select IDT_IN_EVERY_STAGE
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select PAGING_IN_CACHE_AS_RAM
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select INTEL_CAR_NEM
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help
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Intel Geminilake support
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if SOC_INTEL_APOLLOLAKE
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config SKIP_CSE_RBP
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config SKIP_CSE_RBP
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bool
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bool
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@ -1,12 +1,5 @@
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config SOC_INTEL_BAYTRAIL
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config SOC_INTEL_BAYTRAIL
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bool
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bool
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help
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Bay Trail M/D part support.
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if SOC_INTEL_BAYTRAIL
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config CPU_SPECIFIC_OPTIONS
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def_bool y
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select ACPI_COMMON_MADT_IOAPIC
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select ACPI_COMMON_MADT_IOAPIC
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select ACPI_COMMON_MADT_LAPIC
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select ACPI_COMMON_MADT_LAPIC
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select ACPI_INTEL_HARDWARE_SLEEP_VALUES
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select ACPI_INTEL_HARDWARE_SLEEP_VALUES
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@ -38,6 +31,10 @@ config CPU_SPECIFIC_OPTIONS
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select CPU_HAS_L2_ENABLE_MSR
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select CPU_HAS_L2_ENABLE_MSR
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select TCO_SPACE_NOT_YET_SPLIT
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select TCO_SPACE_NOT_YET_SPLIT
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select USE_DDR3
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select USE_DDR3
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help
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Bay Trail M/D part support.
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if SOC_INTEL_BAYTRAIL
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config VBOOT
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config VBOOT
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select VBOOT_MUST_REQUEST_DISPLAY
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select VBOOT_MUST_REQUEST_DISPLAY
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@ -1,12 +1,5 @@
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config SOC_INTEL_BRASWELL
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config SOC_INTEL_BRASWELL
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bool
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bool
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help
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Braswell M/D part support.
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if SOC_INTEL_BRASWELL
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config CPU_SPECIFIC_OPTIONS
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def_bool y
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select ACPI_COMMON_MADT_IOAPIC
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select ACPI_COMMON_MADT_IOAPIC
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select ACPI_COMMON_MADT_LAPIC
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select ACPI_COMMON_MADT_LAPIC
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select ACPI_INTEL_HARDWARE_SLEEP_VALUES
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select ACPI_INTEL_HARDWARE_SLEEP_VALUES
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@ -44,6 +37,10 @@ config CPU_SPECIFIC_OPTIONS
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select SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT
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select SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT
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select NO_CBFS_MCACHE
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select NO_CBFS_MCACHE
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select TCO_SPACE_NOT_YET_SPLIT
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select TCO_SPACE_NOT_YET_SPLIT
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help
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Braswell M/D part support.
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if SOC_INTEL_BRASWELL
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config DCACHE_BSP_STACK_SIZE
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config DCACHE_BSP_STACK_SIZE
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hex
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hex
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@ -1,60 +1,5 @@
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config SOC_INTEL_CANNONLAKE_BASE
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config SOC_INTEL_CANNONLAKE_BASE
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bool
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bool
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config SOC_INTEL_COFFEELAKE
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bool
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select SOC_INTEL_CANNONLAKE_BASE
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select FSP_USES_CB_STACK
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select HAVE_EXP_X86_64_SUPPORT
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select HAVE_INTEL_FSP_REPO
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select HECI_DISABLE_USING_SMM
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select INTEL_CAR_NEM
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select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
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config SOC_INTEL_WHISKEYLAKE
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bool
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select SOC_INTEL_CANNONLAKE_BASE
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select FSP_USES_CB_STACK
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select HAVE_INTEL_FSP_REPO
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select HECI_DISABLE_USING_SMM
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select INTEL_CAR_NEM_ENHANCED
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select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
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config SOC_INTEL_COMETLAKE
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bool
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select SOC_INTEL_CANNONLAKE_BASE
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select FSP_USES_CB_STACK
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select HAVE_INTEL_FSP_REPO
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select INTEL_CAR_NEM_ENHANCED
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select PMC_IPC_ACPI_INTERFACE if DISABLE_HECI1_AT_PRE_BOOT
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select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
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select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC
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select SOC_INTEL_COMMON_BASECODE
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select SOC_INTEL_COMMON_BASECODE_RAMTOP
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config SOC_INTEL_COMETLAKE_1
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bool
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select SOC_INTEL_COMETLAKE
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config SOC_INTEL_COMETLAKE_2
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bool
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select SOC_INTEL_COMETLAKE
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config SOC_INTEL_COMETLAKE_S
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bool
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select SOC_INTEL_COMETLAKE
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config SOC_INTEL_COMETLAKE_V
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bool
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select SOC_INTEL_COMETLAKE
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config SOC_INTEL_CANNONLAKE_PCH_H
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bool
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if SOC_INTEL_CANNONLAKE_BASE
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config CPU_SPECIFIC_OPTIONS
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def_bool y
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select ACPI_INTEL_HARDWARE_SLEEP_VALUES
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select ACPI_INTEL_HARDWARE_SLEEP_VALUES
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select ACPI_NHLT
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select ACPI_NHLT
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select ARCH_X86
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select ARCH_X86
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@ -124,6 +69,58 @@ config CPU_SPECIFIC_OPTIONS
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select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
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select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
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select X86_CLFLUSH_CAR
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select X86_CLFLUSH_CAR
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config SOC_INTEL_COFFEELAKE
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bool
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select SOC_INTEL_CANNONLAKE_BASE
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select FSP_USES_CB_STACK
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select HAVE_EXP_X86_64_SUPPORT
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select HAVE_INTEL_FSP_REPO
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select HECI_DISABLE_USING_SMM
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select INTEL_CAR_NEM
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select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
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config SOC_INTEL_WHISKEYLAKE
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bool
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select SOC_INTEL_CANNONLAKE_BASE
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select FSP_USES_CB_STACK
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select HAVE_INTEL_FSP_REPO
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select HECI_DISABLE_USING_SMM
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select INTEL_CAR_NEM_ENHANCED
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select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
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config SOC_INTEL_COMETLAKE
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bool
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select SOC_INTEL_CANNONLAKE_BASE
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select FSP_USES_CB_STACK
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select HAVE_INTEL_FSP_REPO
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select INTEL_CAR_NEM_ENHANCED
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select PMC_IPC_ACPI_INTERFACE if DISABLE_HECI1_AT_PRE_BOOT
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select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
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select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC
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select SOC_INTEL_COMMON_BASECODE
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select SOC_INTEL_COMMON_BASECODE_RAMTOP
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config SOC_INTEL_COMETLAKE_1
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bool
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select SOC_INTEL_COMETLAKE
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config SOC_INTEL_COMETLAKE_2
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bool
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select SOC_INTEL_COMETLAKE
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config SOC_INTEL_COMETLAKE_S
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bool
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select SOC_INTEL_COMETLAKE
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config SOC_INTEL_COMETLAKE_V
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bool
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select SOC_INTEL_COMETLAKE
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config SOC_INTEL_CANNONLAKE_PCH_H
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bool
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if SOC_INTEL_CANNONLAKE_BASE
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config MAX_CPUS
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config MAX_CPUS
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int
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int
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default 20 if SOC_INTEL_CANNONLAKE_PCH_H && SOC_INTEL_COMETLAKE
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default 20 if SOC_INTEL_CANNONLAKE_PCH_H && SOC_INTEL_COMETLAKE
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@ -2,17 +2,6 @@
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config SOC_INTEL_DENVERTON_NS
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config SOC_INTEL_DENVERTON_NS
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bool
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bool
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help
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Intel Denverton-NS SoC support
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if SOC_INTEL_DENVERTON_NS
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config CPU_INTEL_NUM_FIT_ENTRIES
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int
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default 1
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config CPU_SPECIFIC_OPTIONS
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def_bool y
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select ARCH_X86
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select ARCH_X86
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select BOOT_DEVICE_SUPPORTS_WRITES
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select BOOT_DEVICE_SUPPORTS_WRITES
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select CACHE_MRC_SETTINGS
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select CACHE_MRC_SETTINGS
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@ -50,6 +39,14 @@ config CPU_SPECIFIC_OPTIONS
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select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
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select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
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select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
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select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
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select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
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select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
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help
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Intel Denverton-NS SoC support
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if SOC_INTEL_DENVERTON_NS
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config CPU_INTEL_NUM_FIT_ENTRIES
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int
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default 1
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config ECAM_MMCONF_BASE_ADDRESS
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config ECAM_MMCONF_BASE_ADDRESS
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default 0xe0000000
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default 0xe0000000
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@ -1,12 +1,5 @@
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config SOC_INTEL_ELKHARTLAKE
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config SOC_INTEL_ELKHARTLAKE
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bool
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bool
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help
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Intel Elkhartlake support
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if SOC_INTEL_ELKHARTLAKE
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config CPU_SPECIFIC_OPTIONS
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def_bool y
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select ACPI_INTEL_HARDWARE_SLEEP_VALUES
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select ACPI_INTEL_HARDWARE_SLEEP_VALUES
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select ARCH_X86
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select ARCH_X86
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select BOOT_DEVICE_SUPPORTS_WRITES
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select BOOT_DEVICE_SUPPORTS_WRITES
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select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
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select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
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select SOC_INTEL_RAPL_DISABLE_VIA_MCHBAR
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select SOC_INTEL_RAPL_DISABLE_VIA_MCHBAR
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select X86_CLFLUSH_CAR
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select X86_CLFLUSH_CAR
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help
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Intel Elkhartlake support
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if SOC_INTEL_ELKHARTLAKE
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config MAX_CPUS
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config MAX_CPUS
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int
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int
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