GOOGLE/SNOW: add edp support to ramstage
Add basic edp support to the ramstage. Not working. Change-Id: I15086e03417edca7426c214e67b51719d8ed9341 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/3055 Tested-by: build bot (Jenkins)
This commit is contained in:
Ronald G. Minnich
parent
765ff76d8f
commit
7576f2515e
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@ -203,7 +203,7 @@ static int s5p_dp_config_video(struct s5p_dp_device *dp,
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video_info->ycbcr_coeff);
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if (s5p_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
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debug("PLL is not locked yet.\n");
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printk(BIOS_DEBUG, "PLL is not locked yet.\n");
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return -ERR_PLL_NOT_UNLOCKED;
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}
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@ -216,7 +216,7 @@ static int s5p_dp_config_video(struct s5p_dp_device *dp,
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} while (get_timer(start) <= STREAM_ON_TIMEOUT);
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if (!timeout) {
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debug("Video Clock Not ok\n");
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printk(BIOS_DEBUG, "Video Clock Not ok\n");
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return -ERR_VIDEO_CLOCK_BAD;
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}
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@ -236,7 +236,7 @@ static int s5p_dp_config_video(struct s5p_dp_device *dp,
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timeout = s5p_dp_is_video_stream_on(dp);
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if (timeout) {
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debug("Video Stream Not on\n");
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printk(BIOS_DEBUG, "Video Stream Not on\n");
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return -ERR_VIDEO_STREAM_BAD;
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}
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@ -253,14 +253,14 @@ static int s5p_dp_enable_rx_to_enhanced_mode(struct s5p_dp_device *dp)
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u8 data;
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if (s5p_dp_read_byte_from_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET, &data)) {
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debug("DPCD read error\n");
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printk(BIOS_DEBUG, "DPCD read error\n");
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return -ERR_DPCD_READ_ERROR1;
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}
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if (s5p_dp_write_byte_to_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET,
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DPCD_ENHANCED_FRAME_EN |
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(data & DPCD_LANE_COUNT_SET_MASK))) {
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debug("DPCD write error\n");
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printk(BIOS_DEBUG, "DPCD write error\n");
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return -ERR_DPCD_WRITE_ERROR1;
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}
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@ -281,13 +281,13 @@ static int s5p_dp_enable_scramble(struct s5p_dp_device *dp)
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if (s5p_dp_read_byte_from_dpcd(dp, DPCD_ADDR_TRAINING_PATTERN_SET,
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&data)) {
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debug("DPCD read error\n");
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printk(BIOS_DEBUG, "DPCD read error\n");
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return -ERR_DPCD_READ_ERROR2;
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}
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if (s5p_dp_write_byte_to_dpcd(dp, DPCD_ADDR_TRAINING_PATTERN_SET,
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(u8)(data & ~DPCD_SCRAMBLING_DISABLED))) {
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debug("DPCD write error\n");
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printk(BIOS_DEBUG, "DPCD write error\n");
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return -ERR_DPCD_WRITE_ERROR2;
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}
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@ -314,10 +314,10 @@ static int s5p_dp_init_dp(struct s5p_dp_device *dp)
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break;
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udelay(5000);
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debug("LCD retry init, attempt=%d ret=%d\n", i, ret);
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printk(BIOS_DEBUG, "LCD retry init, attempt=%d ret=%d\n", i, ret);
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}
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if (i == DP_INIT_TRIES) {
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debug("LCD initialization failed, ret=%d\n", ret);
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printk(BIOS_DEBUG, "LCD initialization failed, ret=%d\n", ret);
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return ret;
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}
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@ -356,7 +356,7 @@ static int s5p_dp_set_lane_lane_pre_emphasis(struct s5p_dp_device *dp,
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writel(reg, &base->ln3_link_trn_ctl);
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break;
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default:
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debug("%s: Invalid lane %d\n", __func__, lane);
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printk(BIOS_DEBUG, "%s: Invalid lane %d\n", __func__, lane);
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return -ERR_INVALID_LANE;
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}
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return 0;
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@ -438,7 +438,7 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp,
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for (lane = 0; lane < max_lane; lane++)
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if (s5p_dp_set_lane_lane_pre_emphasis(dp,
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PRE_EMPHASIS_LEVEL_0, lane)) {
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debug("Unable to set pre emphasis level\n");
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printk(BIOS_DEBUG, "Unable to set pre emphasis level\n");
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return -ERR_PRE_EMPHASIS_LEVELS;
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}
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@ -451,14 +451,14 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp,
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if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
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(dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
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debug("Rx Max Link Rate is abnormal :%x !\n",
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printk(BIOS_DEBUG, "Rx Max Link Rate is abnormal :%x !\n",
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dp->link_train.link_rate);
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/* Not Retrying */
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return -ERR_LINK_RATE_ABNORMAL;
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}
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if (dp->link_train.lane_count == 0) {
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debug("Rx Max Lane count is abnormal :%x !\n",
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printk(BIOS_DEBUG, "Rx Max Lane count is abnormal :%x !\n",
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dp->link_train.lane_count);
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/* Not retrying */
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return -ERR_MAX_LANE_COUNT_ABNORMAL;
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@ -487,7 +487,7 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp,
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/* Get hardware link training status */
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data = readl(&base->dp_hw_link_training);
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if (data != 0) {
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debug(" H/W link training failure: 0x%x\n", data);
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printk(BIOS_DEBUG, " H/W link training failure: 0x%x\n", data);
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return -ERR_LINK_TRAINING_FAILURE;
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}
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@ -521,14 +521,14 @@ int dp_controller_init(struct s5p_dp_device *dp_device, unsigned *wait_ms)
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power_enable_dp_phy();
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ret = s5p_dp_init_dp(dp);
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if (ret) {
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debug("%s: Could not initialize dp\n", __func__);
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printk(BIOS_DEBUG, "%s: Could not initialize dp\n", __func__);
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return ret;
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}
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ret = s5p_dp_hw_link_training(dp, dp->video_info->lane_count,
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dp->video_info->link_rate);
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if (ret) {
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debug("unable to do link train\n");
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printk(BIOS_DEBUG, "unable to do link train\n");
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return ret;
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}
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/* Minimum delay after H/w Link training */
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@ -536,13 +536,13 @@ int dp_controller_init(struct s5p_dp_device *dp_device, unsigned *wait_ms)
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ret = s5p_dp_enable_scramble(dp);
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if (ret) {
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debug("unable to set scramble mode\n");
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printk(BIOS_DEBUG, "unable to set scramble mode\n");
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return ret;
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}
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ret = s5p_dp_enable_rx_to_enhanced_mode(dp);
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if (ret) {
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debug("unable to set enhanced mode\n");
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printk(BIOS_DEBUG, "unable to set enhanced mode\n");
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return ret;
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}
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@ -557,7 +557,7 @@ int dp_controller_init(struct s5p_dp_device *dp_device, unsigned *wait_ms)
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s5p_dp_init_video(dp);
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ret = s5p_dp_config_video(dp, dp->video_info);
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if (ret) {
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debug("unable to config video\n");
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printk(BIOS_DEBUG, "unable to config video\n");
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return ret;
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}
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@ -250,6 +250,7 @@ void s5p_dp_config_video_slave_mode(struct s5p_dp_device *dp,
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void s5p_dp_wait_hw_link_training_done(struct s5p_dp_device *dp);
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/* startup and init */
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struct exynos5_fimd_panel;
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void fb_init(vidinfo_t *panel_info, void *lcdbase, struct exynos5_fimd_panel *pd);
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int dp_controller_init(struct s5p_dp_device *dp_device, unsigned *wait_ms);
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int lcd_ctrl_init(vidinfo_t *panel_info, struct exynos5_fimd_panel *panel_data, void *lcdbase);
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@ -19,6 +19,8 @@
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#include "cpu/samsung/exynos5250/fimd.h"
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#include "s5p-dp-core.h"
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#include <console/console.h>
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void s5p_dp_reset(struct s5p_dp_device *dp)
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{
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u32 reg;
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@ -127,7 +129,7 @@ int s5p_dp_init_analog_func(struct s5p_dp_device *dp)
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start = get_timer(0);
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while (s5p_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
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if (get_timer(start) > PLL_LOCK_TIMEOUT) {
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debug("%s: PLL is not locked yet\n", __func__);
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printk(BIOS_DEBUG, "%s: PLL is not locked yet\n", __func__);
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return -1;
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}
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}
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@ -174,6 +176,9 @@ int s5p_dp_start_aux_transaction(struct s5p_dp_device *dp)
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/* Enable AUX CH operation */
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setbits_le32(&base->aux_ch_ctl_2, AUX_EN);
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printk(BIOS_DEBUG, "%s: base: 0x%p, &base->aux_ch_ctl_2: 0x%p, aux_ch_ctl_2: 0x%08x\n",
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__func__, base, &base->aux_ch_ctl_2, readl(&base->aux_ch_ctl_2));
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/* Is AUX CH command reply received? */
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reg = readl(&base->dp_int_sta);
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while (!(reg & RPLY_RECEIV))
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@ -184,6 +189,7 @@ int s5p_dp_start_aux_transaction(struct s5p_dp_device *dp)
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/* Clear interrupt source for AUX CH access error */
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reg = readl(&base->dp_int_sta);
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printk(BIOS_DEBUG, "%s: dp_int_sta: 0x%02x\n", __func__, reg);
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if (reg & AUX_ERR) {
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writel(AUX_ERR, &base->dp_int_sta);
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return -1;
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@ -192,7 +198,7 @@ int s5p_dp_start_aux_transaction(struct s5p_dp_device *dp)
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/* Check AUX CH error access status */
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reg = readl(&base->dp_int_sta);
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if ((reg & AUX_STATUS_MASK) != 0) {
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debug("AUX CH error happens: %d\n\n",
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printk(BIOS_DEBUG, "AUX CH error happens: %d\n\n",
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reg & AUX_STATUS_MASK);
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return -1;
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}
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@ -241,7 +247,7 @@ int s5p_dp_write_byte_to_dpcd(struct s5p_dp_device *dp,
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if (retval == 0)
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break;
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else
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debug("Aux Transaction fail!\n");
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printk(BIOS_DEBUG, "Aux Transaction fail!\n");
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}
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return retval;
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@ -284,7 +290,7 @@ int s5p_dp_read_byte_from_dpcd(struct s5p_dp_device *dp,
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if (retval == 0)
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break;
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else
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debug("Aux Transaction fail!\n");
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printk(BIOS_DEBUG, "Aux Transaction fail!\n");
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}
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/* Read data buffer */
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@ -359,7 +365,7 @@ int s5p_dp_is_slave_video_stream_clock_on(struct s5p_dp_device *dp)
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reg = readl(&base->sys_ctl_2);
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if (reg & CHA_STA) {
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debug("Input stream clk is changing\n");
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printk(BIOS_DEBUG, "Input stream clk is changing\n");
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return -1;
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}
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@ -433,7 +439,7 @@ int s5p_dp_is_video_stream_on(struct s5p_dp_device *dp)
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} while (get_timer(start) <= STREAM_ON_TIMEOUT);
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if (i != 4) {
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debug("s5p_dp_is_video_stream_on timeout\n");
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printk(BIOS_DEBUG, "s5p_dp_is_video_stream_on timeout\n");
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return -1;
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}
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@ -31,6 +31,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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# select MMCONF_SUPPORT
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select EXYNOS_DISPLAYPORT
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select CHROMEOS
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select DRIVER_TI_TPS65090
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config MAINBOARD_DIR
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string
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@ -18,13 +18,22 @@
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <device/i2c.h>
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#include <drivers/ti/tps65090/tps65090.h>
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#include <cbmem.h>
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#include <delay.h>
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#include <arch/cache.h>
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#include <arch/exception.h>
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#include <arch/gpio.h>
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#include <cpu/samsung/exynos5250/clk.h>
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#include <cpu/samsung/exynos5250/cpu.h>
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#include <cpu/samsung/exynos5250/gpio.h>
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#include <cpu/samsung/exynos5250/power.h>
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#include <arch/cache.h>
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#include <cpu/samsung/exynos5-common/i2c.h>
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#include <cpu/samsung/exynos5-common/s5p-dp-core.h>
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/* convenient shorthand (in MB) */
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#define DRAM_START (CONFIG_SYS_SDRAM_BASE >> 20)
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@ -35,7 +44,8 @@ void hardwaremain(int boot_complete);
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void main(void)
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{
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console_init();
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printk(BIOS_INFO, "hello from ramstage; now with deluxe exception handling.\n");
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printk(BIOS_INFO,
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"hello from ramstage; now with deluxe exception handling.\n");
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/* set up coreboot tables */
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high_tables_size = CONFIG_COREBOOT_TABLES_SIZE;
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@ -54,7 +64,8 @@ void main(void)
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dcache_invalidate_all();
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dcache_mmu_enable();
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/* this is going to move, but we must have it now and we're not sure where */
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/* this is going to move, but we must have it now and we're
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* not sure where */
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exception_init();
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const unsigned epll_hz = 192000000;
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@ -68,3 +79,173 @@ void main(void)
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hardwaremain(0);
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}
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/* TODO: transplanted DP stuff, clean up once we have something that works */
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static enum exynos5_gpio_pin dp_pd_l = GPIO_Y25; /* active low */
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static enum exynos5_gpio_pin dp_rst_l = GPIO_X15; /* active low */
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static enum exynos5_gpio_pin dp_hpd = GPIO_X07; /* active high */
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static void exynos_dp_bridge_setup(void)
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{
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exynos_pinmux_config(PERIPH_ID_DPHPD, 0);
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gpio_set_value(dp_pd_l, 1);
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gpio_cfg_pin(dp_pd_l, EXYNOS_GPIO_OUTPUT);
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gpio_set_pull(dp_pd_l, EXYNOS_GPIO_PULL_NONE);
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gpio_set_value(dp_rst_l, 0);
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gpio_cfg_pin(dp_rst_l, EXYNOS_GPIO_OUTPUT);
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gpio_set_pull(dp_rst_l, EXYNOS_GPIO_PULL_NONE);
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udelay(10);
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gpio_set_value(dp_rst_l, 1);
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udelay(90000); /* FIXME: this might be unnecessary */
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}
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static void exynos_dp_bridge_init(void)
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{
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/* De-assert PD (and possibly RST) to power up the bridge */
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gpio_set_value(dp_pd_l, 1);
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gpio_set_value(dp_rst_l, 1);
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/*
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* We need to wait for 90ms after bringing up the bridge since
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* there is a phantom "high" on the HPD chip during its
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* bootup. The phantom high comes within 7ms of de-asserting
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* PD and persists for at least 15ms. The real high comes
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* roughly 50ms after PD is de-asserted. The phantom high
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* makes it hard for us to know when the NXP chip is up.
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*/
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udelay(90000); /* FIXME: this might be unnecessary */
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}
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static int exynos_dp_hotplug(void)
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{
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int x = gpio_get_value(dp_hpd);
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/* Check HPD. If it's high, we're all good. */
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// if (gpio_get_value(dp_hpd))
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// return 0;
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printk(BIOS_DEBUG, "%s: dp_hpd: 0x%02x\n", __func__, x);
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if (x)
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return 0;
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return -1;
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}
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static void exynos_dp_reset(void)
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{
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gpio_set_value(dp_pd_l, 0);
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gpio_set_value(dp_rst_l, 0);
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/* paranoid delay period (300ms) */
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udelay(300 * 1000);
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}
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#define LCD_T5_DELAY_MS 10
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#define LCD_T6_DELAY_MS 10
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static void snow_backlight_pwm(void)
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{
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/*Configure backlight PWM as a simple output high (100% brightness) */
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gpio_direction_output(GPIO_B20, 1);
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udelay(LCD_T6_DELAY_MS * 1000);
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}
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static void snow_backlight_en(void)
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{
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/* * Configure GPIO for LCD_BL_EN */
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gpio_direction_output(GPIO_X30, 1);
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}
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#define TPS69050_BUS 4 /* Snow-specific */
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#define FET1_CTRL 0x0f
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#define FET6_CTRL 0x14
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static void snow_lcd_vdd(void)
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{
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/* Enable FET6, lcd panel */
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tps65090_fet_enable(TPS69050_BUS, FET6_CTRL);
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}
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static void snow_backlight_vdd(void)
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{
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/* Enable FET1, backlight */
|
||||
tps65090_fet_enable(TPS69050_BUS, FET1_CTRL);
|
||||
udelay(LCD_T5_DELAY_MS * 1000);
|
||||
}
|
||||
|
||||
//static struct video_info smdk5250_dp_config = {
|
||||
static struct video_info snow_dp_video_info = {
|
||||
/* FIXME: fix video_info struct to use const for name */
|
||||
.name = (char *)"eDP-LVDS NXP PTN3460",
|
||||
|
||||
.h_sync_polarity = 0,
|
||||
.v_sync_polarity = 0,
|
||||
.interlaced = 0,
|
||||
|
||||
.color_space = COLOR_RGB,
|
||||
.dynamic_range = VESA,
|
||||
.ycbcr_coeff = COLOR_YCBCR601,
|
||||
.color_depth = COLOR_8,
|
||||
|
||||
.link_rate = LINK_RATE_2_70GBPS,
|
||||
.lane_count = LANE_COUNT2,
|
||||
};
|
||||
|
||||
/* FIXME: move some place more appropriate */
|
||||
#define EXYNOS5250_DP1_BASE 0x145b0000
|
||||
#define SNOW_MAX_DP_TRIES 5
|
||||
|
||||
/* this happens after cpu_init where exynos resources are set */
|
||||
static void mainboard_init(device_t dev)
|
||||
{
|
||||
int dp_tries;
|
||||
unsigned int wait_ms;
|
||||
struct s5p_dp_device dp_device = {
|
||||
.base = (struct exynos5_dp *)EXYNOS5250_DP1_BASE,
|
||||
.video_info = &snow_dp_video_info,
|
||||
};
|
||||
|
||||
i2c_init(TPS69050_BUS, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
|
||||
i2c_init(7, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
|
||||
|
||||
snow_lcd_vdd();
|
||||
do {
|
||||
udelay(50);
|
||||
} while (!exynos_dp_hotplug());
|
||||
|
||||
exynos_dp_bridge_setup();
|
||||
for (dp_tries = 1; dp_tries <= SNOW_MAX_DP_TRIES; dp_tries++) {
|
||||
if (wait_ms) {
|
||||
udelay(wait_ms);
|
||||
wait_ms = 0;
|
||||
}
|
||||
|
||||
exynos_dp_bridge_init();
|
||||
if (exynos_dp_hotplug()) {
|
||||
exynos_dp_reset();
|
||||
continue;
|
||||
}
|
||||
|
||||
if (dp_controller_init(&dp_device, &wait_ms))
|
||||
continue;
|
||||
|
||||
snow_backlight_vdd();
|
||||
snow_backlight_pwm();
|
||||
snow_backlight_en();
|
||||
/* if we're here, we're successful */
|
||||
break;
|
||||
}
|
||||
|
||||
if (dp_tries > SNOW_MAX_DP_TRIES)
|
||||
printk(BIOS_ERR, "%s: Failed to set up displayport\n", __func__);
|
||||
}
|
||||
|
||||
static void mainboard_enable(device_t dev)
|
||||
{
|
||||
dev->ops->init = &mainboard_init;
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
.name = "Samsung/Google ARM Chromebook",
|
||||
.enable_dev = mainboard_enable,
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in New Issue