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soc/amd/picasso: remove PICASSO_ACPI_IO_BASE Kconfig option 

This was the only I/O base address in Kconfig, no board changed it and
if a board changed it, it needs to make sure that it won't overlap with
other I/O resources, so just use the same value as constant in the
define instead of the value from Kconfig. Also remove the PICASSO_
prefix from ACPI_IO_BASE.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7ea62f1101ddefa8785da92de5ba2aaf7945694a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Felix Held 2021-02-04 21:31:49 +01:00
parent 74bc46c4db
commit 757d645cb0
3 changed files with 7 additions and 13 deletions
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6
src/soc/amd/picasso/Kconfig
View File

@ -263,12 +263,6 @@ config SERIRQ_CONTINUOUS_MODE
Set this option to y for serial IRQ in continuous mode. Set this option to y for serial IRQ in continuous mode.
Otherwise it is in quiet mode. Otherwise it is in quiet mode.
config PICASSO_ACPI_IO_BASE
hex
default 0x400
help
Base address for the ACPI registers.
config CONSOLE_UART_BASE_ADDRESS config CONSOLE_UART_BASE_ADDRESS
depends on CONSOLE_SERIAL && AMD_SOC_CONSOLE_UART depends on CONSOLE_SERIAL && AMD_SOC_CONSOLE_UART
hex hex

2
src/soc/amd/picasso/acpi.c
View File

@ -94,7 +94,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
{ {
const struct soc_amd_picasso_config *cfg = config_of_soc(); const struct soc_amd_picasso_config *cfg = config_of_soc();
printk(BIOS_DEBUG, "pm_base: 0x%04x\n", PICASSO_ACPI_IO_BASE); printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE);
fadt->sci_int = 9; /* IRQ 09 - ACPI SCI */ fadt->sci_int = 9; /* IRQ 09 - ACPI SCI */

12
src/soc/amd/picasso/include/soc/iomap.h
View File

@ -72,15 +72,15 @@
/* I/O Ranges */ /* I/O Ranges */
#define ACPI_SMI_CTL_PORT 0xb2 #define ACPI_SMI_CTL_PORT 0xb2
#define PICASSO_ACPI_IO_BASE CONFIG_PICASSO_ACPI_IO_BASE #define ACPI_IO_BASE 0x400
#define ACPI_PM_EVT_BLK (PICASSO_ACPI_IO_BASE + 0x00) /* 4 bytes */ #define ACPI_PM_EVT_BLK (ACPI_IO_BASE + 0x00) /* 4 bytes */
#define ACPI_PM1_STS (ACPI_PM_EVT_BLK + 0x00) /* 2 bytes */ #define ACPI_PM1_STS (ACPI_PM_EVT_BLK + 0x00) /* 2 bytes */
#define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02) /* 2 bytes */ #define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02) /* 2 bytes */
#define ACPI_PM1_CNT_BLK (PICASSO_ACPI_IO_BASE + 0x04) /* 2 bytes */ #define ACPI_PM1_CNT_BLK (ACPI_IO_BASE + 0x04) /* 2 bytes */
#define ACPI_PM_TMR_BLK (PICASSO_ACPI_IO_BASE + 0x08) /* 4 bytes */ #define ACPI_PM_TMR_BLK (ACPI_IO_BASE + 0x08) /* 4 bytes */
#define ACPI_CPU_CONTROL (PICASSO_ACPI_IO_BASE + 0x13) #define ACPI_CPU_CONTROL (ACPI_IO_BASE + 0x13)
/* doc says 0x14 for GPE0_BLK but FT5 only works with 0x20 */ /* doc says 0x14 for GPE0_BLK but FT5 only works with 0x20 */
#define ACPI_GPE0_BLK (PICASSO_ACPI_IO_BASE + 0x20) /* 8 bytes */ #define ACPI_GPE0_BLK (ACPI_IO_BASE + 0x20) /* 8 bytes */
#define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00) /* 4 bytes */ #define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00) /* 4 bytes */
#define ACPI_GPE0_EN (ACPI_GPE0_BLK + 0x04) /* 4 bytes */ #define ACPI_GPE0_EN (ACPI_GPE0_BLK + 0x04) /* 4 bytes */
#define NCP_ERR 0xf0 #define NCP_ERR 0xf0