YhLu's patch from January 18th. This part is mostly cleaning up
dead code and adding a few fixmes. Signed-off-by: Yinghai Lu <yinghai.lu@amd.com> Signed-off-by: Ed Swierk <eswierk@arastra.com> Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ward Vandewege <ward@gnu.org> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2594 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Yinghai Lu
Stefan Reinauer
parent
47cb7c71c9
commit
75812a66bb
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@ -485,6 +485,14 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
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* [31:26] Reserved
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*/
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PCI_ADDR(0, 0x18, 2, 0x98), 0xfc00ffff, 0x00000000,
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/* MCA NB Status Low reg */
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PCI_ADDR(0, 0x18, 3, 0x48), 0x00f00000, 0x00000000,
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/* MCA NB Status high reg */
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PCI_ADDR(0, 0x18, 3, 0x4c), 0x01801e8c, 0x00000000,
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/* MCA NB address Low reg */
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PCI_ADDR(0, 0x18, 3, 0x50), 0x00000007, 0x00000000,
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/* MCA NB address high reg */
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PCI_ADDR(0, 0x18, 3, 0x54), 0xffffff00, 0x00000000,
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/* DRAM Scrub Control Register
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* F3:0x58
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* [ 4: 0] DRAM Scrube Rate
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@ -2334,6 +2342,16 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
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/* And if necessary toggle the the reset on the dimms by hand */
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memreset(controllers, ctrl);
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/* We need to wait a mimmium of 20 MEMCLKS to enable the InitDram */
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#if 0
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print_debug("prepare to InitDram:");
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for(i=0; i<100; i++) {
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print_debug_hex32(i);
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print_debug("\b\b\b\b\b\b\b\b");
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}
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print_debug("\r\n");
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#endif
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for(i = 0; i < controllers; i++) {
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uint32_t dcl, dch;
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if (!controller_present(ctrl + i))
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@ -79,16 +79,13 @@ static inline void print_t(const char *strval)
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*/
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#if 1
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static void setup_resource_map(const unsigned int *register_values, int max)
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{
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int i;
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for(i = 0; i < max; i += 3) {
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device_t dev;
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unsigned where;
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unsigned long reg;
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dev = register_values[i] & ~0xff;
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where = register_values[i] & 0xff;
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reg = pci_read_config32(dev, where);
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@ -97,7 +94,6 @@ static void setup_resource_map(const unsigned int *register_values, int max)
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pci_write_config32(dev, where, reg);
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}
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}
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#endif
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static int controller_present(const struct mem_controller *ctrl)
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{
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@ -635,218 +631,13 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in
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- poll the DctAccessDone untio it = 1
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*/
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#if 0
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static const unsigned int index_register_values[] = {
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/* Output Driver Compensation Control Register
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* Index: 0x00
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* [ 1: 0] CkeDrvStren (CKE Drive Strength)
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* 00 = 1.0x
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* 01 = 1.25x
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* 10 = 1.5x (Default)
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* 11 = 2.0x
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* [ 3: 2] reserved
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* [ 5: 4] CsOdtDrvStren (CS/ODT Drive Strength)
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* 00 = 1.0x
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* 01 = 1.25x
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* 10 = 1.5x (Default)
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* 11 = 2.0x
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* [ 7: 6] reserved
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* [ 9: 8] AddrCmdDrvStren (Address/Command Drive Strength)
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* 00 = 1.0x
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* 01 = 1.25x
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* 10 = 1.5x (Default)
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* 11 = 2.0x
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* [11:10] reserved
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* [13:12] ClkDrvStren (MEMCLK Drive Strength)
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* 00 = 0.75x
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* 01 = 1.0x Default)
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* 10 = 1.25x
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* 11 = 1.5x
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* [15:14] reserved
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* [17:16] DataDrvStren (Data Drive Strength)
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* 00 = 0.75x
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* 01 = 1.0x Default)
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* 10 = 1.25x
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* 11 = 1.5x
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* [19:18] reserved
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* [21:20] DqsDrvStren (DQS Drive Strength)
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* 00 = 0.75x
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* 01 = 1.0x Default)
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* 10 = 1.25x
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* 11 = 1.5x
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* [27:22] reserved
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* [29:28] ProcOdt ( Processor On-die Termination)
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* 00 = 300 ohms +/- 20%
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* 01 = 150 ohms +/- 20%
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* 10 = 75 ohms +/- 20%
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* 11 = reserved
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* [31:30] reserved
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*/
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0x00, 0xcfcccccc, 0x00000000,
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0x20, 0xcfcccccc, 0x00000000,
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/* Write Data Timing Low Control Register
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* Index 0x01
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* [ 5: 0] WrDatTimeByte0 (Write Data Byte 0 Timing Control)
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* 000000 = no delay
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* 000001 = 1/96 MEMCLK delay
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* 000010 = 2/96 MEMCLK delay
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* ...
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* 101111 = 47/96 MEMCLK delay
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* 11xxxx = reserved
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* [ 7: 6] reserved
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* [13: 8] WrDatTimeByte1 (Write Data Byte 1 Timing Control)
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* [15:14] reserved
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* [21:16] WrDatTimeByte2 (Write Data Byte 2 Timing Control)
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* [23:22] reserved
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* [29:24] WrDatTimeByte3 (Write Data Byte 3 Timing Control)
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* [31:30] reserved
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*/
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0x01, 0xc0c0c0c0, 0x00000000,
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0x21, 0xc0c0c0c0, 0x00000000,
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/* Write Data Timing High Control Register
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* Index 0x02
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* [ 5: 0] WrDatTimeByte4 (Write Data Byte 4 Timing Control)
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* [ 7: 6] reserved
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* [13: 8] WrDatTimeByte5 (Write Data Byte 5 Timing Control)
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* [15:14] reserved
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* [21:16] WrDatTimeByte6 (Write Data Byte 6 Timing Control)
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* [23:22] reserved
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* [29:24] WrDatTimeByte7 (Write Data Byte 7 Timing Control)
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* [31:30] reserved
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*/
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0x02, 0xc0c0c0c0, 0x00000000,
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0x22, 0xc0c0c0c0, 0x00000000,
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/* Write Data ECC Timing Control Register
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* Index 0x03
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* [ 5: 0] WrChkTime (Write Data ECC Timing Control)
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* 000000 = no delay
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* 000001 = 1/96 MEMCLK delay
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* 000010 = 2/96 MEMCLK delay
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* ...
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* 101111 = 47/96 MEMCLK delay
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* 11xxxx = reserved
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* [31: 6] reserved
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*/
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0x03, 0x000000c0, 0x00000000,
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0x23, 0x000000c0, 0x00000000,
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/* Address Timing Control Register
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* Index 0x04
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* [ 4: 0] CkeFineDelay (CKE Fine Delay)
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* 00000 = no delay
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* 00001 = 1/64 MEMCLK delay
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* 00010 = 2/64 MEMCLK delay
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* ...
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* 11111 = 31/64 MEMCLK delay
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* [ 5: 5] CkeSetup (CKE Setup Time)
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* 0 = 1/2 MEMCLK
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* 1 = 1 MEMCLK
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* [ 7: 6] reserved
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* [12: 8] CsOdtFineDelay (CS/ODT Fine Delay)
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* 00000 = no delay
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* 00001 = 1/64 MEMCLK delay
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* 00010 = 2/64 MEMCLK delay
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* ...
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* 11111 = 31/64 MEMCLK delay
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* [13:13] CsOdtSetup (CS/ODT Setup Time)
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* 0 = 1/2 MEMCLK
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* 1 = 1 MEMCLK
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* [15:14] reserved
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* [20:16] AddrCmdFineDelay (Address/Command Fine Delay)
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* 00000 = no delay
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* 00001 = 1/64 MEMCLK delay
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* 00010 = 2/64 MEMCLK delay
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* ...
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* 11111 = 31/64 MEMCLK delay
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* [21:21] AddrCmdSetup (Address/Command Setup Time)
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* 0 = 1/2 MEMCLK
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* 1 = 1 MEMCLK
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* [31:22] reserved
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*/
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0x04, 0xffc0c0c0, 0x00000000,
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0x24, 0xffc0c0c0, 0x00000000,
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/* Read DQS Timing Low Control Register
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* Index 0x05
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* [ 5: 0] RdDqsTimeByte0 (Read DQS Byte 0 Timing Control)
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* 000000 = no delay
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* 000001 = 1/96 MEMCLK delay
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* 000010 = 2/96 MEMCLK delay
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* ...
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* 101111 = 47/96 MEMCLK delay
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* 11xxxx = reserved
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* [ 7: 6] reserved
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* [13: 8] RdDqsTimeByte1 (Read DQS Byte 1 Timing Control)
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* [15:14] reserved
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* [21:16] RdDqsTimeByte2 (Read DQS Byte 2 Timing Control)
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* [23:22] reserved
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* [29:24] RdDqsTimeByte3 (Read DQS Byte 3 Timing Control)
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* [31:30] reserved
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*/
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0x05, 0xc0c0c0c0, 0x00000000,
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0x25, 0xc0c0c0c0, 0x00000000,
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/* Read DQS Timing High Control Register
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* Index 0x06
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* [ 5: 0] RdDqsTimeByte4 (Read DQS Byte 4 Timing Control)
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* [ 7: 6] reserved
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* [13: 8] RdDqsTimeByte5 (Read DQS Byte 5 Timing Control)
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* [15:14] reserved
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* [21:16] RdDqsTimeByte6 (Read DQS Byte 6 Timing Control)
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* [23:22] reserved
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* [29:24] RdDqsTimeByte7 (Read DQS Byte 7 Timing Control)
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* [31:30] reserved
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*/
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0x06, 0xc0c0c0c0, 0x00000000,
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0x26, 0xc0c0c0c0, 0x00000000,
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/* Read DQS ECC Timing Control Register
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* Index 0x07
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* [ 5: 0] RdDqsTimeCheck (Read DQS ECC Timing Control)
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* 000000 = no delay
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* 000001 = 1/96 MEMCLK delay
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* 000010 = 2/96 MEMCLK delay
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* ...
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* 101111 = 47/96 MEMCLK delay
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* 11xxxx = reserved
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* [31: 6] reserved
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*/
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0x07, 0x000000c0, 0x00000000,
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0x27, 0x000000c0, 0x00000000,
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/* DQS Receiver Enable Timing Control Register
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* Index 0x10, 0x13, 0x16, 0x19,
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* [ 7: 0] Dqs RcvEnDelay (DQS Receiver Enable Delay)
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* 0x00 = 0 ps
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* 0x01 = 50 ps
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* 0x02 = 100 ps
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* ...
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* 0xae = 8.7 ns
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* 0xaf-0xff = reserved
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* [31: 6] reserved
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*/
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0x10, 0x000000ff, 0x00000000,
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0x13, 0x000000ff, 0x00000000,
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0x16, 0x000000ff, 0x00000000,
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0x19, 0x000000ff, 0x00000000,
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0x30, 0x000000ff, 0x00000000,
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0x33, 0x000000ff, 0x00000000,
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0x36, 0x000000ff, 0x00000000,
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0x39, 0x000000ff, 0x00000000,
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};
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#endif
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int i;
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int max;
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#if 1
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if (!controller_present(ctrl)) {
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// print_debug("No memory controller present\r\n");
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sysinfo->ctrl_present[ctrl->node_id] = 0;
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return;
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}
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#endif
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sysinfo->ctrl_present[ctrl->node_id] = 1;
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print_spew("setting up CPU");
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@ -865,20 +656,6 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in
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pci_write_config32(dev, where, reg);
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}
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#if 0
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// for index regs
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max = sizeof(index_register_values)/sizeof(index_register_values[0]);
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for(i = 0; i < max; i += 3) {
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unsigned long reg;
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unsigned index;
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index = register_values[i];
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reg = pci_read_config32_index_wait(ctrl->f2, DRAM_CTRL_ADDI_DATA_OFFSET, index);
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reg &= register_values[i+1];
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reg |= register_values[i+2];
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pci_write_config32_index_wait(ctrl->f2, DRAM_CTRL_ADDI_DATA_OFFSET, index, reg);
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}
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#endif
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print_spew("done.\r\n");
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}
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@ -889,6 +666,19 @@ static int is_dual_channel(const struct mem_controller *ctrl)
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return dcl & DCL_Width128;
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}
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static int is_opteron(const struct mem_controller *ctrl)
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{
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/* Test to see if I am an Opteron.
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* FIXME Testing dual channel capability is correct for now
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* but a beter test is probably required.
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* m2 and s1g1 support dual channel too. but only support unbuffered dimm
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*/
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#warning "FIXME implement a better test for opterons"
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uint32_t nbcap;
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nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
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return !!(nbcap & NBCAP_128Bit);
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}
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static int is_registered(const struct mem_controller *ctrl)
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{
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/* Test to see if we are dealing with registered SDRAM.
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@ -1456,6 +1246,20 @@ static long spd_handle_unbuffered_dimms(const struct mem_controller *ctrl, long
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}
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}
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if (is_opteron(ctrl)) {
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#if 0
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if ( registered != (dimm_mask & ((1<<DIMM_SOCKETS)-1)) ) {
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dimm_mask &= (registered | (registered << DIMM_SOCKETS) ); //disable unbuffed dimm
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// die("Mixed buffered and registered dimms not supported");
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}
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//By yhlu for debug M2, s1g1 can do dual channel, but it use unbuffer DIMM
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if (!registered) {
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die("Unbuffered Dimms not supported on Opteron");
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}
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#endif
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}
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dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
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dcl &= ~DCL_UnBuffDimm;
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meminfo->is_registered = 1;
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@ -1852,7 +1656,6 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *
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if (latencies < 0) goto hw_error;
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if (latencies == 0) {
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continue;
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// goto dimm_err;
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}
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/* Compute the lowest cas latency supported */
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@ -1966,23 +1769,6 @@ static int update_dimm_Trfc(const struct mem_controller *ctrl, const struct mem_
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uint32_t dth;
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int value;
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#if 0
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int value2;
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value = spd_read_byte(ctrl->channel0[i], SPD_TRFC);
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if (value < 0) return -1;
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value2 = spd_read_byte(ctrl->channel0[i], SPD_TRC -1);
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if(value2 & 1) value += 256;
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value <<= 2;
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value += convert_to_1_4(value2>>1);
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if (value == 0) {
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value = param->tRFC;
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}
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value *= 10;
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clocks = (value + param->divisor - 1)/param->divisor;
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#endif
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//get the cs_size --> logic dimm size
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value = spd_read_byte(ctrl->channel0[i], SPD_PRI_WIDTH);
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if (value < 0) {
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@ -1997,7 +1783,6 @@ static int update_dimm_Trfc(const struct mem_controller *ctrl, const struct mem_
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old_clocks = ((dth >> (DTH_TRFC0_SHIFT+i*3)) & DTH_TRFC_MASK);
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if (old_clocks >= clocks) { // some one did it?
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// clocks = old_clocks;
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return 1;
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}
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dth &= ~(DTH_TRFC_MASK << (DTH_TRFC0_SHIFT+i*3));
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@ -2072,7 +1857,6 @@ static int update_dimm_Tras(const struct mem_controller *ctrl, const struct mem_
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dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
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old_clocks = ((dtl >> DTL_TRAS_SHIFT) & DTL_TRAS_MASK) + DTL_TRAS_BASE;
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if (old_clocks >= clocks) { // someone did it?
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// clocks = old_clocks;
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return 1;
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}
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dtl &= ~(DTL_TRAS_MASK << DTL_TRAS_SHIFT);
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@ -2397,6 +2181,7 @@ static void set_max_async_latency(const struct mem_controller *ctrl, const struc
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dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
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dch &= ~(DCH_MaxAsyncLat_MASK << DCH_MaxAsyncLat_SHIFT);
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//FIXME: We need to use Max of DqsRcvEnDelay + 6ns here: After trainning and get that from index reg 0x10, 0x13, 0x16, 0x19, 0x30, 0x33, 0x36, 0x39
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async_lat = 6+6;
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@ -2684,7 +2469,6 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl, struct sy
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long dimm_mask;
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#if 1
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if (!sysinfo->ctrl_present[ctrl->node_id]) {
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// print_debug("No memory controller present\r\n");
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return;
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}
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#endif
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@ -2852,6 +2636,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl, str
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#if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
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unsigned cpu_f0_f1[8];
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/* FIXME: How about 32 node machine later? */
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tsc_t tsc, tsc0[8];
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print_debug_addr("sdram_enable: tsc0[8]: ", &tsc0[0]);
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@ -2886,6 +2671,14 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl, str
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/* We need to wait a mimmium of 20 MEMCLKS to enable the InitDram */
|
||||
memreset(controllers, ctrl);
|
||||
#if 0
|
||||
print_debug("prepare to InitDram:");
|
||||
for(i=0; i<10; i++) {
|
||||
print_debug_hex32(i);
|
||||
print_debug("\b\b\b\b\b\b\b\b");
|
||||
}
|
||||
print_debug("\r\n");
|
||||
#endif
|
||||
|
||||
for(i = 0; i < controllers; i++) {
|
||||
uint32_t dcl, dch;
|
||||
|
|
@ -3016,10 +2809,6 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl, str
|
|||
sysinfo->mem_trained[i] = 0x80; // mem need to be trained
|
||||
}
|
||||
|
||||
#if 0
|
||||
dump_pci_devices();
|
||||
dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98);
|
||||
#endif
|
||||
|
||||
#if MEM_TRAIN_SEQ == 0
|
||||
#if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
|
||||
|
|
@ -3056,11 +2845,6 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl, str
|
|||
wait_all_core0_mem_trained(sysinfo);
|
||||
#endif
|
||||
|
||||
#if 0
|
||||
dump_pci_devices();
|
||||
dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98);
|
||||
#endif
|
||||
|
||||
}
|
||||
static void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, const uint16_t *spd_addr)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -107,15 +107,6 @@ static unsigned Get_MCTSysAddr(const struct mem_controller *ctrl, unsigned cs_i
|
|||
|
||||
static unsigned Get_RcvrSysAddr(const struct mem_controller * ctrl, unsigned channel, unsigned cs_idx, struct sys_info *sysinfo)
|
||||
{
|
||||
#if 0
|
||||
//get SB_64MuxedMode
|
||||
uint32_t dword;
|
||||
dword = pci_read_config32(ctrl->f2, DRAM_CTRL_MISC);
|
||||
if((dword & DCM_Mode64BitMux) == DCM_Mode64BitMux) {
|
||||
if(channel) cs_idx += 4; // translate Receiver number to Chipsel
|
||||
}
|
||||
#endif
|
||||
|
||||
return Get_MCTSysAddr(ctrl, cs_idx, sysinfo);
|
||||
|
||||
}
|
||||
|
|
@ -181,43 +172,6 @@ static void set_FSBASE(uint32_t addr_hi)
|
|||
|
||||
}
|
||||
|
||||
#if 0
|
||||
static void write_mem(uint32_t addr_hi, uint32_t addr_lo, uint32_t value)
|
||||
{
|
||||
if(addr_hi == 0) {
|
||||
*((uint32_t *)addr_lo) = value;
|
||||
return;
|
||||
}
|
||||
|
||||
set_FSBASE(addr_hi);
|
||||
|
||||
__asm__ volatile (
|
||||
"movl %1, %%fs:(%0)\n\t"
|
||||
:: "a" (addr_lo), "b" (value)
|
||||
);
|
||||
|
||||
}
|
||||
|
||||
static uint32_t read_mem(uint32_t addr_hi, uint32_t addr_lo)
|
||||
{
|
||||
unsigned value;
|
||||
if(addr_hi == 0) {
|
||||
value = *((uint32_t *)addr_lo);
|
||||
return value;
|
||||
}
|
||||
|
||||
set_FSBASE(addr_hi);
|
||||
|
||||
__asm__ volatile (
|
||||
"movl %%fs:(%1), %0\n\t"
|
||||
:"=b"(value): "a" (addr_lo)
|
||||
);
|
||||
|
||||
return value;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
static unsigned ChipSelPresent(const struct mem_controller *ctrl, unsigned cs_idx, struct sys_info *sysinfo)
|
||||
{
|
||||
unsigned enabled;
|
||||
|
|
@ -233,6 +187,7 @@ static unsigned ChipSelPresent(const struct mem_controller *ctrl, unsigned cs_id
|
|||
|
||||
static unsigned RcvrRankEnabled(const struct mem_controller *ctrl, int channel, int cs_idx, unsigned is_Width128, struct sys_info *sysinfo)
|
||||
{
|
||||
/* FIXME: process 64Muxed */
|
||||
if(!is_Width128) {
|
||||
if(channel) return 0; // no channel b
|
||||
}
|
||||
|
|
@ -701,6 +656,7 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st
|
|||
|
||||
/* Program current Receiver enable delay */
|
||||
pci_write_config32_index_wait(ctrl->f2, 0x98, index, RcvrEnDly);
|
||||
/* FIXME: 64bit MUX */
|
||||
|
||||
if(is_Width128) {
|
||||
/* Program current Receiver enable delay chaannel b */
|
||||
|
|
@ -1164,6 +1120,7 @@ static unsigned TrainDQSPos(const struct mem_controller *ctrl, unsigned channel,
|
|||
|
||||
for(ChipSel = 0; ChipSel < 8; ChipSel++) { //logical register chipselects 0..7
|
||||
print_debug_dqs("\t\t\t\tTrainDQSPos: 11 ChipSel ", ChipSel, 4);
|
||||
//FIXME: process 64MUXedMode
|
||||
if(!ChipSelPresent(ctrl, ChipSel, sysinfo)) continue;
|
||||
BanksPresent = 1;
|
||||
|
||||
|
|
@ -1454,6 +1411,7 @@ static unsigned TrainDQSRdWrPos(const struct mem_controller *ctrl, struct sys_in
|
|||
}
|
||||
channel++;
|
||||
if(!is_Width128){
|
||||
//FIXME: 64MuxMode??
|
||||
channel++; // skip channel if 64-bit mode
|
||||
}
|
||||
}
|
||||
|
|
@ -2030,11 +1988,15 @@ static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sy
|
|||
wait_till_sysinfo_in_ram(); // use pci to get it
|
||||
|
||||
if(sysinfox->mem_trained[nodeid] == 0x80) {
|
||||
#if 0
|
||||
sysinfo->tom_k = sysinfox->tom_k;
|
||||
sysinfo->tom2_k = sysinfox->tom2_k;
|
||||
sysinfo->meminfo[nodeid].is_Width128 = sysinfox->meminfo[nodeid].is_Width128;
|
||||
sysinfo->mem_trained[nodeid] = sysinfox->mem_trained[nodeid];
|
||||
memcpy(&sysinfo->ctrl[nodeid], &sysinfox->ctrl[nodeid], sizeof(struct mem_controller));
|
||||
#else
|
||||
memcpy(sysinfo, sysinfox, DCACHE_RAM_GLOBAL_VAR_SIZE);
|
||||
#endif
|
||||
set_top_mem_ap(sysinfo->tom_k, sysinfo->tom2_k); // keep the ap's tom consistent with bsp's
|
||||
#if CONFIG_AP_CODE_IN_CAR == 0
|
||||
print_debug("CODE IN ROM AND RUN ON NODE:"); print_debug_hex8(nodeid); print_debug("\r\n");
|
||||
|
|
|
|||
Loading…
Reference in New Issue