From 7587526583bf7820ffcb09edcce92bbd48237382 Mon Sep 17 00:00:00 2001 From: Zhuohao Lee Date: Mon, 8 Jun 2020 15:37:23 +0800 Subject: [PATCH] palkia: separate the gpio pins control for the second touch There are two touch screen controllers on the Palkia device. One is on the lid; another is on the base. To support the different control path (for example: turning off the base's touch event when we don't want to use it however still keeping the lid's touch event), we use the different gpio pins to control the second touch. As a result, we need to modify the devicetree to adopt this change. With this change, we can control the primary and secondary touch screen controller respectively. BUG=b:149714955 TEST=lid/base touch screen works correctly Change-Id: I1f896e334e51c78300af724cbef8d57641ae5612 Signed-off-by: Zhuohao Lee Reviewed-on: https://review.coreboot.org/c/coreboot/+/42185 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/hatch/variants/palkia/gpio.c | 4 ++++ src/mainboard/google/hatch/variants/palkia/overridetree.cb | 4 ++-- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/hatch/variants/palkia/gpio.c b/src/mainboard/google/hatch/variants/palkia/gpio.c index 04f1d8561e..115a593c85 100644 --- a/src/mainboard/google/hatch/variants/palkia/gpio.c +++ b/src/mainboard/google/hatch/variants/palkia/gpio.c @@ -45,6 +45,10 @@ static const struct pad_config gpio_table[] = { /* C23 : UART2_CTS# ==> NC */ PAD_NC(GPP_C23, NONE), + /* D4 : USI_BASE_REPORT_EN */ + PAD_CFG_GPO(GPP_D4, 0, DEEP), + /* D10 : GPP_D10 ==> EN_PP3300_DX_BASE_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_D10, 0, DEEP), /* D16 : USI_INT_L */ PAD_CFG_GPI_APIC(GPP_D16, NONE, PLTRST, LEVEL, INVERT), diff --git a/src/mainboard/google/hatch/variants/palkia/overridetree.cb b/src/mainboard/google/hatch/variants/palkia/overridetree.cb index 31017bc01d..73cf0f21b9 100644 --- a/src/mainboard/google/hatch/variants/palkia/overridetree.cb +++ b/src/mainboard/google/hatch/variants/palkia/overridetree.cb @@ -136,12 +136,12 @@ chip soc/intel/cannonlake "ACPI_IRQ_EDGE_LOW(GPP_C7_IRQ)" register "generic.probed" = "1" register "generic.enable_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D10)" register "generic.enable_delay_ms" = "12" register "generic.enable_off_delay_ms" = "10" register "generic.has_power_resource" = "1" register "generic.stop_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)" + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" register "generic.stop_delay_ms" = "15" register "generic.stop_off_delay_ms" = "5" register "hid_desc_reg_offset" = "0x01"