diff --git a/configs/config.ocp_tiogapass b/configs/config.ocp_tiogapass
new file mode 100644
index 0000000000..ca0a5b791a
--- /dev/null
+++ b/configs/config.ocp_tiogapass
@@ -0,0 +1,5 @@
+CONFIG_VENDOR_OCP=y
+CONFIG_BOARD_OCP_TIOGAPASS=y
+CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
+CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y
+CONFIG_CPU_UCODE_BINARIES="3rdparty/intel-microcode/intel-ucode/06-55-04"
diff --git a/src/mainboard/ocp/Kconfig b/src/mainboard/ocp/Kconfig
new file mode 100644
index 0000000000..b748129e81
--- /dev/null
+++ b/src/mainboard/ocp/Kconfig
@@ -0,0 +1,16 @@
+if VENDOR_OCP
+
+choice
+	prompt "Mainboard model"
+
+source "src/mainboard/ocp/*/Kconfig.name"
+
+endchoice
+
+source "src/mainboard/ocp/*/Kconfig"
+
+config MAINBOARD_VENDOR
+	string
+	default "Open Compute Project"
+
+endif # VENDOR_OCP
diff --git a/src/mainboard/ocp/Kconfig.name b/src/mainboard/ocp/Kconfig.name
new file mode 100644
index 0000000000..f5d8d0a8eb
--- /dev/null
+++ b/src/mainboard/ocp/Kconfig.name
@@ -0,0 +1,2 @@
+config VENDOR_OCP
+	bool "Open Compute Project"
diff --git a/src/mainboard/ocp/tiogapass/Kconfig b/src/mainboard/ocp/tiogapass/Kconfig
new file mode 100644
index 0000000000..dfa8f54275
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/Kconfig
@@ -0,0 +1,45 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2019 - 2020 Intel Corporation.
+## Copyright (C) 2019 - 2020 Facebook Inc
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+if BOARD_OCP_TIOGAPASS
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select ADD_FSP_BINARIES
+	select BOARD_ROMSIZE_KB_32768
+	select HAVE_ACPI_TABLES
+	select SOC_INTEL_XEON_SP
+	select MAINBOARD_USES_FSP2_0
+	select FSP_CAR
+
+config MAINBOARD_DIR
+	string
+	default "ocp/tiogapass"
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "TiogaPass"
+
+config MAINBOARD_FAMILY
+	string
+	default "TiogaPass"
+
+config FMDFILE
+	string
+	default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd"
+
+endif # BOARD_OCP_TIOGAPASS
diff --git a/src/mainboard/ocp/tiogapass/Kconfig.name b/src/mainboard/ocp/tiogapass/Kconfig.name
new file mode 100644
index 0000000000..e1bf821575
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_OCP_TIOGAPASS
+	bool "TiogaPass"
diff --git a/src/mainboard/ocp/tiogapass/Makefile.inc b/src/mainboard/ocp/tiogapass/Makefile.inc
new file mode 100644
index 0000000000..f5ea5911f9
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/Makefile.inc
@@ -0,0 +1,22 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2019 - 2020 Intel Corporation.
+## Copyright (C) 2019 - 2020 Facebook Inc
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+ramstage-y += ramstage.c
+ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c
+
+CPPFLAGS_common += -Isrc/mainboard/$(MAINBOARDDIR)/
+CPPFLAGS_common += -I$(CONFIG_FSP_HEADER_PATH)
diff --git a/src/mainboard/ocp/tiogapass/acpi/platform.asl b/src/mainboard/ocp/tiogapass/acpi/platform.asl
new file mode 100644
index 0000000000..e349cf337a
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/acpi/platform.asl
@@ -0,0 +1,382 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 - 2020 Intel Corporation.
+ * Copyright (C) 2019 - 2020 Facebook Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* Enable ACPI _SWS methods */
+#include <soc/intel/common/acpi/acpi_wake_source.asl>
+
+Name (_S0, Package (0x04) // mandatory system state
+{
+	0x00, 0x00, 0x00, 0x00
+})
+
+Name (_S5, Package (0x04)  // mandatory system state
+{
+	0x07, 0x00, 0x00, 0x00
+})
+
+/* The APM port can be used for generating software SMIs */
+OperationRegion (APMP, SystemIO, 0xb2, 2)
+Field (APMP, ByteAcc, NoLock, Preserve)
+{
+	APMC, 8,	// APM command
+	APMS, 8		// APM status
+}
+
+/* Port 80 POST */
+OperationRegion (DBG0, SystemIO, 0x80, 0x02)
+Field (DBG0, ByteAcc, Lock, Preserve)
+{
+	IO80, 8,
+	IO81, 8
+}
+
+/* IO-Trap at 0x800.
+ * This is the ACPI->SMI communication interface.
+ */
+OperationRegion (IO_T, SystemIO, 0x800, 0x10)
+Field (IO_T, ByteAcc, NoLock, Preserve)
+{
+	Offset (0x8),
+	TRP0, 8		/* IO-Trap at 0x808 */
+}
+
+OperationRegion (PSYS, SystemMemory, 0x6D081000, 0x0400)
+Field (PSYS, ByteAcc, NoLock, Preserve)
+{
+	PLAT,   32,  // Platform ID
+
+	// IOAPIC
+	APC0,   1,   // PCH IOAPIC Enable
+	AP00,   1,   // PC00 IOAPIC Enable
+	AP01,   1,   // PC01 IOAPIC Enable
+	AP02,   1,   // PC02 IOAPIC Enable
+	AP03,   1,   // PC03 IOAPIC Enable
+	AP04,   1,   // PC04 IOAPIC Enable
+	AP05,   1,   // PC05 IOAPIC Enable
+	AP06,   1,   // PC06 IOAPIC Enable
+	AP07,   1,   // PC07 IOAPIC Enable
+	AP08,   1,   // PC08 IOAPIC Enable
+	AP09,   1,   // PC09 IOAPIC Enable
+	AP10,   1,   // PC10 IOAPIC Enable
+	AP11,   1,   // PC11 IOAPIC Enable
+	AP12,   1,   // PC12 IOAPIC Enable
+	AP13,   1,   // PC13 IOAPIC Enable
+	AP14,   1,   // PC14 IOAPIC Enable
+	AP15,   1,   // PC15 IOAPIC Enable
+	AP16,   1,   // PC16 IOAPIC Enable
+	AP17,   1,   // PC17 IOAPIC Enable
+	AP18,   1,   // PC18 IOAPIC Enable
+	AP19,   1,   // PC19 IOAPIC Enable
+	AP20,   1,   // PC20 IOAPIC Enable
+	AP21,   1,   // PC21 IOAPIC Enable
+	AP22,   1,   // PC22 IOAPIC Enable
+	AP23,   1,   // PC23 IOAPIC Enable
+	RESA,   7,
+	SKOV,   1,   // Override Socket APIC Id
+	RES0,   7,
+
+	// Power Management
+	TPME,   1,
+	CSEN,   1,
+	C3EN,   1,
+	C6EN,   1,
+	C7EN,   1,
+	MWOS,   1,
+	PSEN,   1,
+	EMCA,   1,
+	HWAL,   2,
+	KPRS,   1,
+	MPRS,   1,
+	TSEN,   1,
+	FGTS,   1,
+	OSCX,   1,
+	RESX,   1,
+
+	// RAS
+	CPHP,   8,
+	IIOP,   8,
+	IIOH,   64,
+	PRBM,   32,
+	P0ID,   32,
+	P1ID,   32,
+	P2ID,   32,
+	P3ID,   32,
+	P4ID,   32,
+	P5ID,   32,
+	P6ID,   32,
+	P7ID,   32,
+	P0BM,   64,
+	P1BM,   64,
+	P2BM,   64,
+	P3BM,   64,
+	P4BM,   64,
+	P5BM,   64,
+	P6BM,   64,
+	P7BM,   64,
+	MEBM,   16,
+	MEBC,   16,
+	CFMM,   32,
+	TSSY,   32,  // TODO: This is TSSZ in system booted from production FW
+	M0BS,   64,
+	M1BS,   64,
+	M2BS,   64,
+	M3BS,   64,
+	M4BS,   64,
+	M5BS,   64,
+	M6BS,   64,
+	M7BS,   64,
+	M0RN,   64,
+	M1RN,   64,
+	M2RN,   64,
+	M3RN,   64,
+	M4RN,   64,
+	M5RN,   64,
+	M6RN,   64,
+	M7RN,   64,
+	SMI0,   32,
+	SMI1,   32,
+	SMI2,   32,
+	SMI3,   32,
+	SCI0,   32,
+	SCI1,   32,
+	SCI2,   32,
+	SCI3,   32,
+	MADD,   64,
+	CUU0,   128,
+	CUU1,   128,
+	CUU2,   128,
+	CUU3,   128,
+	CUU4,   128,
+	CUU5,   128,
+	CUU6,   128,
+	CUU7,   128,
+	CPSP,   8,
+	ME00,   128,
+	ME01,   128,
+	ME10,   128,
+	ME11,   128,
+	ME20,   128,
+	ME21,   128,
+	ME30,   128,
+	ME31,   128,
+	ME40,   128,
+	ME41,   128,
+	ME50,   128,
+	ME51,   128,
+	ME60,   128,
+	ME61,   128,
+	ME70,   128,
+	ME71,   128,
+	MESP,   16,
+	LDIR,   64,
+	PRID,   32,
+	AHPE,   8,
+
+	// VTD
+	DHRD,   192,
+	ATSR,   192,
+	RHSA,   192,
+
+	// SR-IOV
+	WSIC,   8,
+	WSIS,   16,
+	WSIB,   8,
+	WSID,   8,
+	WSIF,   8,
+	WSTS,   8,
+	WHEA,   8,
+
+	// BIOS Guard
+	BGMA,   64,
+	BGMS,   8,
+	BGIO,   16,
+	BGIL,   8,
+	CNBS,   8,
+
+	// USB3
+	XHMD,   8,
+	SBV1,   8,
+	SBV2,   8,
+
+	// HWPM
+	HWEN,   2,
+	ACEN,   1,
+	HWPI,   1,
+	RES1,   4,
+
+	// IIO
+	BB00,   8,
+	BB01,   8,
+	BB02,   8,
+	BB03,   8,
+	BB04,   8,
+	BB05,   8,
+	BB06,   8,
+	BB07,   8,
+	BB08,   8,
+	BB09,   8,
+	BB10,   8,
+	BB11,   8,
+	BB12,   8,
+	BB13,   8,
+	BB14,   8,
+	BB15,   8,
+	BB16,   8,
+	BB17,   8,
+	BB18,   8,
+	BB19,   8,
+	BB20,   8,
+	BB21,   8,
+	BB22,   8,
+	BB23,   8,
+	BB24,   8,
+	BB25,   8,
+	BB26,   8,
+	BB27,   8,
+	BB28,   8,
+	BB29,   8,
+	BB30,   8,
+	BB31,   8,
+	BB32,   8,
+	BB33,   8,
+	BB34,   8,
+	BB35,   8,
+	BB36,   8,
+	BB37,   8,
+	BB38,   8,
+	BB39,   8,
+	BB40,   8,
+	BB41,   8,
+	BB42,   8,
+	BB43,   8,
+	BB44,   8,
+	BB45,   8,
+	BB46,   8,
+	BB47,   8,
+	SGEN,   8,
+	SG00,   8,
+	SG01,   8,
+	SG02,   8,
+	SG03,   8,
+	SG04,   8,
+	SG05,   8,
+	SG06,   8,
+	SG07,   8,
+
+	// Performance
+	CLOD,   8,
+
+	// XTU
+	XTUB,   32,
+	XTUS,   32,
+	XMBA,   32,
+	DDRF,   8,
+	RT3S,   8,
+	RTP0,   8,
+	RTP3,   8,
+
+	// FPGA
+	FBB0,   8,
+	FBB1,   8,
+	FBB2,   8,
+	FBB3,   8,
+	FBB4,   8,
+	FBB5,   8,
+	FBB6,   8,
+	FBB7,   8,
+	FBL0,   8,
+	FBL1,   8,
+	FBL2,   8,
+	FBL3,   8,
+	FBL4,   8,
+	FBL5,   8,
+	FBL6,   8,
+	FBL7,   8,
+	P0FB,   8,
+	P1FB,   8,
+	P2FB,   8,
+	P3FB,   8,
+	P4FB,   8,
+	P5FB,   8,
+	P6FB,   8,
+	P7FB,   8,
+	FMB0,   32,
+	FMB1,   32,
+	FMB2,   32,
+	FMB3,   32,
+	FMB4,   32,
+	FMB5,   32,
+	FMB6,   32,
+	FMB7,   32,
+	FML0,   32,
+	FML1,   32,
+	FML2,   32,
+	FML3,   32,
+	FML4,   32,
+	FML5,   32,
+	FML6,   32,
+	FML7,   32,
+	FKPB,   32,
+	FKB0,   8,
+	FKB1,   8,
+	FKB2,   8,
+	FKB3,   8,
+	FKB4,   8,
+	FKB5,   8,
+	FKB6,   8,
+	FKB7,   8
+}
+
+/* SMI I/O Trap */
+Method (TRAP, 1, Serialized)
+{
+	Store (Arg0, SMIF)	// SMI Function
+	Store (0, TRP0)		// Generate trap
+	Return (SMIF)		// Return value of SMI handler
+}
+
+/*
+ * The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local Apic/IOAPIC configuration.
+ */
+
+Method (_PIC, 1)
+{
+	/* Remember the OS' IRQ routing choice. */
+	Store (Arg0, PICM)
+}
+
+/*
+ * The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method (_PTS, 1)
+{
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method (_WAK, 1)
+{
+	Return (Package (){ 0, 0 })
+}
diff --git a/src/mainboard/ocp/tiogapass/acpi_tables.c b/src/mainboard/ocp/tiogapass/acpi_tables.c
new file mode 100644
index 0000000000..c4dda3b357
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/acpi_tables.c
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ * Copyright (C) 2014 - 2020 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <intelblocks/acpi.h>
+#include <soc/acpi.h>
+
+extern const unsigned char AmlCode[];
+
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+	acpi_init_gnvs(gnvs);
+}
diff --git a/src/mainboard/ocp/tiogapass/board.fmd b/src/mainboard/ocp/tiogapass/board.fmd
new file mode 100644
index 0000000000..1e3fda7e8b
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/board.fmd
@@ -0,0 +1,11 @@
+FLASH 32M {
+	SI_ALL@0x0 0xa36000 {
+		SI_DESC@0x0 0x1000
+		SI_ME@0x1000 0xa23000
+		PLATFORM_DATA@0xa26000 0x10000
+	}
+	SI_BIOS@0x1000000 0x1000000 {
+		FMAP@0x0 0x800
+		COREBOOT(CBFS)@0x800 0xfff800
+	}
+}
diff --git a/src/mainboard/ocp/tiogapass/board_info.txt b/src/mainboard/ocp/tiogapass/board_info.txt
new file mode 100644
index 0000000000..e86f78f6c3
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/board_info.txt
@@ -0,0 +1,5 @@
+Board name: TiogaPass
+Category: server
+ROM protocol: SPI
+ROM socketed: yes
+Release year: 2018
diff --git a/src/mainboard/ocp/tiogapass/devicetree.cb b/src/mainboard/ocp/tiogapass/devicetree.cb
new file mode 100644
index 0000000000..46311d9823
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/devicetree.cb
@@ -0,0 +1,91 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2019 - 2020 Intel Corporation.
+## Copyright (C) 2019 - 2020 Facebook Inc
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+chip soc/intel/xeon_sp
+
+	register "pirqa_routing" = "PCH_IRQ11"
+	register "pirqb_routing" = "PCH_IRQ10"
+	register "pirqc_routing" = "PCH_IRQ11"
+	register "pirqd_routing" = "PCH_IRQ11"
+	register "pirqe_routing" = "PCH_IRQ11"
+	register "pirqf_routing" = "PCH_IRQ11"
+	register "pirqg_routing" = "PCH_IRQ11"
+	register "pirqh_routing" = "PCH_IRQ11"
+
+	# configure device interrupt routing
+	register "ir00_routing" = "0x3210" # IR00, Dev31
+	register "ir01_routing" = "0x3210" # IR01, Dev30
+	register "ir02_routing" = "0x3210" # IR02, Dev29
+	register "ir03_routing" = "0x3210" # IR03, Dev28
+	register "ir04_routing" = "0x3210" # IR04, Dev27
+
+	# configure interrupt polarity control
+	register "ipc0" = "0x00ff4000" # IPC0, PIRQA-H (IRQ16-23) should always be ActiveLow
+	register "ipc1" = "0x00000000" # IPC1
+	register "ipc2" = "0x00000000" # IPC2
+	register "ipc3" = "0x00000000" # IPC3
+
+	# configure MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT_CORES msrs
+	# FB production turbo_ratio_limit is 0x1f1f1f2022222325
+	register "turbo_ratio_limit" = "0x1b1b1b1d20222325"
+	# FB production turbo_ratio_limit_cores is 0x1c1812100c080402
+	register "turbo_ratio_limit_cores" = "0x1c1814100c080402"
+
+	# configure PSTATE_REQ_RATIO for MSR_IA32_PERF_CTRL
+	register "pstate_req_ratio" = "0xa"
+
+	# configure VTD
+	register "vtd_support" = "1"
+	register "coherency_support" = "1"
+	register "ats_support" = "1"
+
+	device cpu_cluster 0 on
+	  device lapic 0 on end
+	end
+
+	device domain 0 on
+		device pci 00.0 on end # Host bridge
+		device pci 04.0 on end # Intel Corporation SkyLake-E CBDMA Registers
+		device pci 04.1 on end # Intel Corporation SkyLake-E CBDMA Registers
+		device pci 04.2 on end # Intel Corporation SkyLake-E CBDMA Registers
+		device pci 04.3 on end # Intel Corporation SkyLake-E CBDMA Registers
+		device pci 04.4 on end # Intel Corporation SkyLake-E CBDMA Registers
+		device pci 04.5 on end # Intel Corporation SkyLake-E CBDMA Registers
+		device pci 04.6 on end # Intel Corporation SkyLake-E CBDMA Registers
+		device pci 04.7 on end # Intel Corporation SkyLake-E CBDMA Registers
+		device pci 05.0 on end # Intel Corporation SkyLake-E MM/Vt-d Configuration Registers
+		device pci 05.2 on end # Intel Corporation Device 2025
+		device pci 05.4 on end # Intel Corporation Device 2026
+		device pci 08.0 on end # Intel Corporation SkyLake-E Ubox Registers
+		device pci 08.1 on end # Intel Corporation SkyLake-E Ubox Registers
+		device pci 08.2 on end # Intel Corporation SkyLake-E Ubox Registers
+		device pci 11.0 on end # Intel Corporation C620 Series Chipset Family MROM 0
+		device pci 11.1 on end # Intel Corporation C620 Series Chipset Family MROM 1
+		device pci 11.5 on end # Intel Corporation C620 Series Chipset Family SSATA Controller [AHCI mode]
+		device pci 14.0 on end # Intel Corporation C620 Series Chipset Family USB 3.0 xHCI Controller
+		device pci 16.0 on end # Intel Corporation C620 Series Chipset Family MEI Controller #1
+		device pci 16.1 on end # Intel Corporation C620 Series Chipset Family MEI Controller #2
+		device pci 16.4 on end # Intel Corporation C620 Series Chipset Family MEI Controller #3
+		device pci 17.0 on end # Intel Corporation C620 Series Chipset Family SATA Controller [AHCI mode]
+		device pci 1c.0 on end # PCI bridge: Intel Corporation C620 Series Chipset Family PCI Express Root Port #1
+		device pci 1c.4 on end # PCI bridge: Intel Corporation C620 Series Chipset Family PCI Express Root Port #5
+		device pci 1f.0 on end # Intel Corporation C621 Series Chipset LPC/eSPI Controller
+		device pci 1f.2 on end # Intel Corporation C620 Series Chipset Family Power Management Controller
+		device pci 1f.4 on end # Intel Corporation C620 Series Chipset Family SMBus
+		device pci 1f.5 on end # Intel Corporation C620 Series Chipset Family SPI Controller
+	end
+end
diff --git a/src/mainboard/ocp/tiogapass/dsdt.asl b/src/mainboard/ocp/tiogapass/dsdt.asl
new file mode 100644
index 0000000000..aca6c4d79b
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/dsdt.asl
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 - 2020 Intel Corporation.
+ * Copyright (C) 2019 - 2020 Facebook Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+
+#include <arch/acpi.h>
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x02,		// DSDT revision: ACPI v2.0 and up
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725	// OEM revision
+)
+{
+	// platform ACPI tables
+	#include "acpi/platform.asl"
+
+	// global NVS and variables
+	#include <soc/intel/xeon_sp/acpi/globalnvs.asl>
+
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	// Xeon-SP ACPI tables
+	Scope (\_SB) {
+		#include <soc/intel/xeon_sp/acpi/uncore.asl>
+	}
+}
diff --git a/src/mainboard/ocp/tiogapass/fadt.c b/src/mainboard/ocp/tiogapass/fadt.c
new file mode 100644
index 0000000000..6962455813
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/fadt.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 - 2020 Intel Corporation.
+ * Copyright (C) 2019 - 2020 Facebook Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <soc/acpi.h>
+
+void motherboard_fill_fadt(acpi_fadt_t *fadt)
+{
+	fadt->reserved = 0;
+	fadt->preferred_pm_profile = PM_ENTERPRISE_SERVER;
+}
diff --git a/src/mainboard/ocp/tiogapass/ramstage.c b/src/mainboard/ocp/tiogapass/ramstage.c
new file mode 100644
index 0000000000..35a7faa99a
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/ramstage.c
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 - 2020 Intel Corporation.
+ * Copyright (C) 2019 - 2020 Facebook Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <soc/ramstage.h>
+
+void mainboard_silicon_init_params(FSPS_UPD *params)
+{
+}
diff --git a/src/mainboard/ocp/tiogapass/romstage.c b/src/mainboard/ocp/tiogapass/romstage.c
new file mode 100644
index 0000000000..c95a69674d
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/romstage.c
@@ -0,0 +1,60 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 - 2020 Intel Corporation.
+ * Copyright (C) 2019 - 2020 Facebook Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <fsp/api.h>
+#include <FspmUpd.h>
+#include <soc/romstage.h>
+
+#include "skxsp_tp_gpio.h"
+#include "skxsp_tp_iio.h"
+
+/*
+* Configure GPIO depend on platform
+*/
+static void mainboard_config_gpios(FSPM_UPD *mupd)
+{
+	mupd->FspmConfig.GpioConfig.GpioTable = (UPD_GPIO_INIT_CONFIG *) tp_gpio_table;
+	mupd->FspmConfig.GpioConfig.NumberOfEntries =
+		sizeof(tp_gpio_table)/sizeof(UPD_GPIO_INIT_CONFIG);
+}
+
+static void mainboard_config_iio(FSPM_UPD *mupd)
+{
+	mupd->FspmConfig.IioBifurcationConfig.IIoBifurcationTable =
+		(UPD_IIO_BIFURCATION_DATA_ENTRY *) tp_iio_bifur_table;
+	mupd->FspmConfig.IioBifurcationConfig.NumberOfEntries =
+		ARRAY_SIZE(tp_iio_bifur_table);
+
+	mupd->FspmConfig.IioPciConfig.ConfigurationTable =
+		(UPD_PCI_PORT_CONFIG *) tp_iio_pci_port_skt0;
+	mupd->FspmConfig.IioPciConfig.NumberOfEntries =
+		ARRAY_SIZE(tp_iio_pci_port_skt0);
+
+	mupd->FspmConfig.PchPciConfig.PciPortConfig =
+		(UPD_PCH_PCIE_PORT *) tp_pch_pci_port_skt0;
+	mupd->FspmConfig.PchPciConfig.NumberOfEntries =
+		ARRAY_SIZE(tp_pch_pci_port_skt0);
+
+	mupd->FspmConfig.PchPciConfig.RootPortFunctionSwapping = 0x00;
+	mupd->FspmConfig.PchPciConfig.PciePllSsc = 0x00;
+}
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	mainboard_config_gpios(mupd);
+	mainboard_config_iio(mupd);
+}
diff --git a/src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h b/src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h
new file mode 100644
index 0000000000..5987caa883
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h
@@ -0,0 +1,1019 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 - 2020 Intel Corporation.
+ * Copyright (C) 2019 - 2020 Facebook Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SKXSP_TP_GPIO_H_
+#define _SKXSP_TP_GPIO_H_
+
+#include <gpio_fsp.h>
+#include <soc/gpio_soc_defs.h>
+
+/*
+ *  OCP TiogaPass Gpio Pad Configuration
+ */
+static const UPD_GPIO_INIT_CONFIG tp_gpio_table[] = {
+	{GPIO_SKL_H_GPP_A0, {
+		GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,    GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_A_0_LPC_RCIN_N_ESPI_ALERT1_N
+	{GPIO_SKL_H_GPP_A1, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_A_1_LAD_0_ESPI_IO_0
+	{GPIO_SKL_H_GPP_A2, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_A_2_LAD_1_ESPI_IO_1
+	{GPIO_SKL_H_GPP_A3, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_A_3_LAD_2_ESPI_IO_2
+	{GPIO_SKL_H_GPP_A4, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_A_4_LAD_3_ESPI_IO_3
+	{GPIO_SKL_H_GPP_A5, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_A_5_LPC_LFRAME_N_ESPI_CS0_N
+	{GPIO_SKL_H_GPP_A6, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_A_6_IRQ_LPC_SERIRQ_ESPI_CS1_N
+	{GPIO_SKL_H_GPP_A7, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_A_7_IRQ_LPC_PIRQA_N_ESPI_ALERT0_N
+	{GPIO_SKL_H_GPP_A8, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_A_8_FM_LPC_CLKRUN_N
+	{GPIO_SKL_H_GPP_A9, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_A_9_CLKOUT_LPC0_ESPI_CLK
+	{GPIO_SKL_H_GPP_A10, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_A_10_CLKOUT_LPC1
+	{GPIO_SKL_H_GPP_A11, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_A_11_FM_LPC_PME_N
+	{GPIO_SKL_H_GPP_A12, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_A_12_BMBUSY_N_SXEXITHLDOFF_N
+	{GPIO_SKL_H_GPP_A13, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_A_13_SUSWARN_N_SUSPWRDNACK
+	{GPIO_SKL_H_GPP_A14, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_A_14_ESPI_RESET_N
+	{GPIO_SKL_H_GPP_A15, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_A_15_SUSACK_N
+	{GPIO_SKL_H_GPP_A16, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_A_16_CLKOUT_LPC2
+	{GPIO_SKL_H_GPP_A17, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_A_17
+	{GPIO_SKL_H_GPP_A18, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_A_18
+	//		{GPIO_SKL_H_GPP_A19, {} }, //GPP_A_19, controlled by ME
+	{GPIO_SKL_H_GPP_A20, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} },//GPP_A_20
+	{GPIO_SKL_H_GPP_A21, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,   GpioOutLow,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_A_21
+	{GPIO_SKL_H_GPP_A22, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_A_22
+	{GPIO_SKL_H_GPP_A23, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_A_23
+
+	{GPIO_SKL_H_GPP_B0,  {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_B_0_CORE_VID_0
+	{GPIO_SKL_H_GPP_B1,  {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_B_1_CORE_VID_1
+	{GPIO_SKL_H_GPP_B2,  {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_B_2_VRALERT_N
+	{GPIO_SKL_H_GPP_B3,  {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_B_3_CPU_GP2
+	{GPIO_SKL_H_GPP_B4,  {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_B_4_CPU_GP3
+	{GPIO_SKL_H_GPP_B5,  {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_B_5_SRCCLKREQ0_N
+	{GPIO_SKL_H_GPP_B6,  {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_B_6_SRCCLKREQ1_N
+	{GPIO_SKL_H_GPP_B7,  {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_B_7_SRCCLKREQ2_N
+	{GPIO_SKL_H_GPP_B8,  {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_B_8_SRCCLKREQ3_N
+	{GPIO_SKL_H_GPP_B9,  {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_B_9_SRCCLKREQ4_N
+	{GPIO_SKL_H_GPP_B10, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_B_10_SRCCLKREQ5_N
+	{GPIO_SKL_H_GPP_B11, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,   GpioOutLow,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_B_11
+	{GPIO_SKL_H_GPP_B12, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_B_12_GLB_RST_WARN_N
+	{GPIO_SKL_H_GPP_B13, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_B_13_RST_PLTRST_N
+	{GPIO_SKL_H_GPP_B14, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_B_14_FM_PCH_BIOS_RCVR_SPKR
+	{GPIO_SKL_H_GPP_B15, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_B_15
+	{GPIO_SKL_H_GPP_B16, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_B_16
+	{GPIO_SKL_H_GPP_B17, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_B_17
+	{GPIO_SKL_H_GPP_B18, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_B_18
+	{GPIO_SKL_H_GPP_B19, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,   GpioOutLow,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_B_19
+	{GPIO_SKL_H_GPP_B20, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_B_20
+	{GPIO_SKL_H_GPP_B21, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_B_21
+	{GPIO_SKL_H_GPP_B22, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_B_22
+	{GPIO_SKL_H_GPP_B23, {
+		GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut,   GpioOutLow,
+		GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_B_23_MEIE_SML1ALRT_N_PHOT_N
+
+//		{GPIO_SKL_H_GPP_C0,  {} }, //GPP_C_0_SMBCLK, controlled by ME
+//		{GPIO_SKL_H_GPP_C1,  {} }, //GPP_C_1_SMBDATA, controlled by ME
+	{GPIO_SKL_H_GPP_C2,  {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_C_2_SMBALERT_N
+//		{GPIO_SKL_H_GPP_C3,  {} }, //GPP_C_3_SML0CLK_IE, controlled by ME
+//		{GPIO_SKL_H_GPP_C4,  {} }, //GPP_C_4_SML0DATA_IE, controlled by ME
+	{GPIO_SKL_H_GPP_C5,  {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+		GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_C_5_SML0ALERT_IE_N
+//		{GPIO_SKL_H_GPP_C6,  {} }, //GPP_C_6_SML1CLK_IE, controlled by ME
+//		{GPIO_SKL_H_GPP_C7,  {} }, //GPP_C_7_SML1DATA_IE, controlled by ME
+	{GPIO_SKL_H_GPP_C8,  {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_C_8
+	{GPIO_SKL_H_GPP_C9,  {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_C_9
+	{GPIO_SKL_H_GPP_C10, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow,
+		GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_C_10
+	{GPIO_SKL_H_GPP_C11, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,	GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_C_11
+	{GPIO_SKL_H_GPP_C12, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_C_12
+	{GPIO_SKL_H_GPP_C13, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_C_13
+	{GPIO_SKL_H_GPP_C14, {
+		GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault,
+		GpioIntLevel | GpioIntSci, GpioResetNormal, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_C_14
+	{GPIO_SKL_H_GPP_C15, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_C_15
+	{GPIO_SKL_H_GPP_C16, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_C_16
+	{GPIO_SKL_H_GPP_C17, {
+		GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_C_17
+	{GPIO_SKL_H_GPP_C18, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_C_18
+	{GPIO_SKL_H_GPP_C19, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_C_19
+//		{GPIO_SKL_H_GPP_C20, {} }, //GPP_C_20, controlled by ME
+	{GPIO_SKL_H_GPP_C21, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_C_21
+	{GPIO_SKL_H_GPP_C22, {
+		GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault,
+		GpioIntLevel | GpioIntSmi, GpioResetNormal, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_C_22
+	{GPIO_SKL_H_GPP_C23, {
+		GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault,
+		GpioIntLevel | GpioIntSmi, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_C_23
+
+	{GPIO_SKL_H_GPP_D0, {
+		GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn,		GpioOutDefault,
+		GpioIntLevel | GpioIntSmi, GpioResetNormal, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_D_0
+	{GPIO_SKL_H_GPP_D1, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_D_1
+	{GPIO_SKL_H_GPP_D2, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_D_2
+	{GPIO_SKL_H_GPP_D3, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_D_3
+	{GPIO_SKL_H_GPP_D4, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,   GpioOutLow,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_D_4
+	{GPIO_SKL_H_GPP_D5, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_D_5
+	{GPIO_SKL_H_GPP_D6, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_D_6
+	{GPIO_SKL_H_GPP_D7, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_D_7
+	{GPIO_SKL_H_GPP_D8, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_D_8
+	{GPIO_SKL_H_GPP_D9, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_D_9_SSATA_DEVSLP3
+	{GPIO_SKL_H_GPP_D10, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_D_10_SSATA_DEVSLP4
+	{GPIO_SKL_H_GPP_D11, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_D_11_SSATA_DEVSLP5
+	{GPIO_SKL_H_GPP_D12, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_D_12_SSATA_SDATAOUT1
+	{GPIO_SKL_H_GPP_D13, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_D_13_SML0BLCK_IE
+	{GPIO_SKL_H_GPP_D14, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_D_14_SML0BDATA_IE
+	{GPIO_SKL_H_GPP_D15, {
+		GpioPadModeNative3, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_D_15_SSATA_SDATAOUT0
+	{GPIO_SKL_H_GPP_D16, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_D_16_SML0BALERT_IE_N
+	{GPIO_SKL_H_GPP_D17, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_D_17
+	{GPIO_SKL_H_GPP_D18, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_D_18
+	{GPIO_SKL_H_GPP_D19, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,   GpioOutLow,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock | GpioOutputStateLock
+		} }, //GPP_D_19
+	{GPIO_SKL_H_GPP_D20, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_D_20_TP_PCH_GPP_D_20
+	{GPIO_SKL_H_GPP_D21, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_D_21_IE_URAT_RX
+	{GPIO_SKL_H_GPP_D22, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_D_22_IE_URAT_TX
+	{GPIO_SKL_H_GPP_D23, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_D_23
+
+	{GPIO_SKL_H_GPP_E0, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntLevel | GpioIntSmi, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_E_0_SATAXPCIE0_SATAGP0
+	{GPIO_SKL_H_GPP_E1, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntLevel | GpioIntSmi, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_E_1_SATAXPCIE1_SATAGP1
+	{GPIO_SKL_H_GPP_E2, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_E_2_SATAXPCIE2_SATAGP2
+	{GPIO_SKL_H_GPP_E3, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_E_3_CPU_GP0
+	{GPIO_SKL_H_GPP_E4, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_E_4_SATA_DEVSLP0
+	{GPIO_SKL_H_GPP_E5, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_E_5_SATA_DEVSLP1
+	{GPIO_SKL_H_GPP_E6, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_E_6_SATA_DEVSLP2
+	{GPIO_SKL_H_GPP_E7, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_E_7_CPU_GP1
+	{GPIO_SKL_H_GPP_E8, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_E_8_SATA_LED_N
+	{GPIO_SKL_H_GPP_E9, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_E_9_USB2_OC0_N
+	{GPIO_SKL_H_GPP_E10, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_E_10_USB2_OC1_N
+	{GPIO_SKL_H_GPP_E11, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_E_11_USB2_OC2_N
+	{GPIO_SKL_H_GPP_E12, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_E_12_USB2_OC3_N
+
+	{GPIO_SKL_H_GPP_F0, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_F_0_SATAXPCIE3_SATAGP3
+	{GPIO_SKL_H_GPP_F1, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_F_1_SATAXPCIE4_SATAGP4
+	{GPIO_SKL_H_GPP_F2, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_F_2_SATAXPCIE5_SATAGP5
+	{GPIO_SKL_H_GPP_F3, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_F_3_SATAXPCIE6_SATAGP6
+	{GPIO_SKL_H_GPP_F4, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_F_4_SATAXPCIE7_SATAGP7
+	{GPIO_SKL_H_GPP_F5, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutLow,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_F_5_SATA_DEVSLP3
+	{GPIO_SKL_H_GPP_F6, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_F_6_SATA_DEVSLP4
+	{GPIO_SKL_H_GPP_F7, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_F_7_SATA_DEVSLP5
+	{GPIO_SKL_H_GPP_F8, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_F_8_SATA_DEVSLP6
+	{GPIO_SKL_H_GPP_F9, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_F_9_SATA_DEVSLP7
+	{GPIO_SKL_H_GPP_F10, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_F_10_SATA_SCLOCK
+	{GPIO_SKL_H_GPP_F11, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_F_11_SATA_SLOAD
+	{GPIO_SKL_H_GPP_F12, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_F_12_SATA_SDATAOUT1
+	{GPIO_SKL_H_GPP_F13, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_F_13_SATA_SDATAOUT0
+	{GPIO_SKL_H_GPP_F14, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_F_14_SSATA_LED_N
+	{GPIO_SKL_H_GPP_F15, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_F_15_USB2_OC4_N
+	{GPIO_SKL_H_GPP_F16, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_F_16_USB2_OC5_N
+	{GPIO_SKL_H_GPP_F17, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_F_17_USB2_OC6_N
+	{GPIO_SKL_H_GPP_F18, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_F_18_USB2_OC7_N
+	{GPIO_SKL_H_GPP_F19, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_F_19_LAN_SMBCLK
+	{GPIO_SKL_H_GPP_F20, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_F_20_LAN_SMBDATA
+	{GPIO_SKL_H_GPP_F21, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_F_21_LAN_SMBALERT_N
+	{GPIO_SKL_H_GPP_F22, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_F_22_SSATA_SCLOCK
+	{GPIO_SKL_H_GPP_F23, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_F_23_SSATA_SLOAD
+
+	{GPIO_SKL_H_GPP_G0, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_G_0_FANTACH0_FANTACH0IE
+	{GPIO_SKL_H_GPP_G1, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_G_1_FANTACH1_FANTACH1IE
+	{GPIO_SKL_H_GPP_G2, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_G_2_FANTACH2_FANTACH2IE
+	{GPIO_SKL_H_GPP_G3, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_G_3_FANTACH3_FANTACH3IE
+	{GPIO_SKL_H_GPP_G4, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_G_4_FANTACH4_FANTACH4IE
+	{GPIO_SKL_H_GPP_G5, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_G_5_FANTACH5_FANTACH5IE
+	{GPIO_SKL_H_GPP_G6, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_G_6_FANTACH6_FANTACH6IE
+	{GPIO_SKL_H_GPP_G7, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_G_7_FANTACH7_FANTACH7IE
+	{GPIO_SKL_H_GPP_G8, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_G_8_FANPWM0_FANPWM0IE
+	{GPIO_SKL_H_GPP_G9, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_G_9_FANPWM1_FANPWM1IE
+	{GPIO_SKL_H_GPP_G10, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_G_10_FANPWM2_FANPWM2IE
+	{GPIO_SKL_H_GPP_G11, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_G_11_FANPWM3_FANPWM3IE
+	{GPIO_SKL_H_GPP_G12, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutLow,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_G_12
+	{GPIO_SKL_H_GPP_G13, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutLow,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_G_13
+	{GPIO_SKL_H_GPP_G14, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutLow,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_G_14
+	{GPIO_SKL_H_GPP_G15, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutLow,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_G_15
+	{GPIO_SKL_H_GPP_G16, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutLow,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_G_16
+	{GPIO_SKL_H_GPP_G17, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_G_17_ADR_COMPLETE
+	{GPIO_SKL_H_GPP_G18, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_G_18_FM_NMI_EVENT_N
+	{GPIO_SKL_H_GPP_G19, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_G_19_FM_SMI_ACTIVE_N
+//		{GPIO_SKL_H_GPP_G20, {} }, //GPP_G_20_SSATA_DEVSLP0, controlled by ME
+	{GPIO_SKL_H_GPP_G21, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_G_21_SSATA_DEVSLP1
+	{GPIO_SKL_H_GPP_G22, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_G_22_SSATA_DEVSLP2
+	{GPIO_SKL_H_GPP_G23, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_G_23_SSATAXPCIE0_SSATAGP0
+
+	{GPIO_SKL_H_GPP_H0, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_H_0_SRCCLKREQ6_N
+	{GPIO_SKL_H_GPP_H1, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_H_1_SRCCLKREQ7_N
+	{GPIO_SKL_H_GPP_H2, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_H_2_SRCCLKREQ8_N
+	{GPIO_SKL_H_GPP_H3, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_H_3_SRCCLKREQ9_N
+	{GPIO_SKL_H_GPP_H4, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_H_4_SRCCLKREQ10_N
+//		{GPIO_SKL_H_GPP_H5,  {} }, //GPP_H_5_SRCCLKREQ11_N
+	{GPIO_SKL_H_GPP_H6, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_H_6_SRCCLKREQ12_N
+	{GPIO_SKL_H_GPP_H7, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_H_7_SRCCLKREQ13_N
+	{GPIO_SKL_H_GPP_H8, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_H_8_SRCCLKREQ14_N
+	{GPIO_SKL_H_GPP_H9, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_H_9_SRCCLKREQ15_N
+//		{GPIO_SKL_H_GPP_H10, {} }, //GPP_H_10_SML2CLK_IE
+//		{GPIO_SKL_H_GPP_H11, {} }, //GPP_H_11_SML2DATA_IE
+	{GPIO_SKL_H_GPP_H12, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_H_12_SML2ALERT_N_IE
+//		{GPIO_SKL_H_GPP_H13, {} }, //GPP_H_13_SML3CLK_IE
+//		{GPIO_SKL_H_GPP_H14, {} }, //GPP_H_14_SML3DATA_IE
+	{GPIO_SKL_H_GPP_H15, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_H_15_SML3ALERT_N_IE
+//		{GPIO_SKL_H_GPP_H16, {} }, //GPP_H_16_SML4CLK_IE
+//		{GPIO_SKL_H_GPP_H17, {} }, //GPP_H_17_SML4DATA_IE
+	{GPIO_SKL_H_GPP_H18, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_H_18_SML4ALERT_N_IE
+	{GPIO_SKL_H_GPP_H19, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_H_19_SSATAXPCIE1_SSATAGP1
+	{GPIO_SKL_H_GPP_H20, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_H_20_SSATAXPCIE2_SSATAGP2
+	{GPIO_SKL_H_GPP_H21, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_H_21_SSATAXPCIE3_SSATAGP3
+	{GPIO_SKL_H_GPP_H22, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_H_22_SSATAXPCIE4_SSATAGP4
+	{GPIO_SKL_H_GPP_H23, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_H_23_SSATAXPCIE5_SSATAGP5
+
+	{GPIO_SKL_H_GPP_I0, {
+		GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_I_0_GBE_TDO
+	{GPIO_SKL_H_GPP_I1, {
+		GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_I_1_GBE_TCK
+	{GPIO_SKL_H_GPP_I2, {
+		GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_I_2_GBE_TMS
+	{GPIO_SKL_H_GPP_I3, {
+		GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_I_3_GBE_TDI
+	{GPIO_SKL_H_GPP_I4, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_I_4_DO_RESET_IN_N
+	{GPIO_SKL_H_GPP_I5, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_I_5_DO_RESET_OUT_N
+	{GPIO_SKL_H_GPP_I6, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_I_6_RESET_DONE
+	{GPIO_SKL_H_GPP_I7, {
+		GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_I_7_JTAG_GBE_TRST_N
+	{GPIO_SKL_H_GPP_I8, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_I_8_GBE_PCI_DIS
+	{GPIO_SKL_H_GPP_I9, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_I_9_GBE_LAN_DIS
+	{GPIO_SKL_H_GPP_I10, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_I_10
+
+	{GPIO_SKL_H_GPP_J0, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_J_0_LAN_LED_P0_0
+	{GPIO_SKL_H_GPP_J1, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_J_1_LAN_LED_P0_1
+	{GPIO_SKL_H_GPP_J2, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_J_2_LAN_LED_P1_0
+	{GPIO_SKL_H_GPP_J3, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_J_3_LAN_LED_P1_1
+	{GPIO_SKL_H_GPP_J4, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_J_4_LAN_LED_P2_0
+	{GPIO_SKL_H_GPP_J5, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_J_5_LAN_LED_P2_1
+	{GPIO_SKL_H_GPP_J6, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_J_6_LAN_LED_P3_0
+	{GPIO_SKL_H_GPP_J7, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_J_7_LAN_LED_P3_1
+	{GPIO_SKL_H_GPP_J8, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_J_8_LAN_I2C_SCL_MDC_P0
+	{GPIO_SKL_H_GPP_J9, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_J_9_LAN_I2C_SDA_MDIO_P0
+	{GPIO_SKL_H_GPP_J10, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_J_10_LAN_I2C_SCL_MDC_P1
+	{GPIO_SKL_H_GPP_J11, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_J_11_LAN_I2C_SDA_MDIO_P1
+	{GPIO_SKL_H_GPP_J12, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_J_12_LAN_I2C_SCL_MDC_P2
+	{GPIO_SKL_H_GPP_J13, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_J_13_LAN_I2C_SDA_MDIO_P2
+	{GPIO_SKL_H_GPP_J14, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_J_14_LAN_I2C_SCL_MDC_P3
+	{GPIO_SKL_H_GPP_J15, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_J_15_LAN_I2C_SDA_MDIO_P3
+	{GPIO_SKL_H_GPP_J16, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_J_16_LAN_SDP_P0_0
+	{GPIO_SKL_H_GPP_J17, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_J_17_LAN_SDP_P0_1
+	{GPIO_SKL_H_GPP_J18, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_J_18_LAN_SDP_P1_0
+	{GPIO_SKL_H_GPP_J19, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_J_19_LAN_SDP_P1_1
+	{GPIO_SKL_H_GPP_J20, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_J_20_LAN_SDP_P2_0
+	{GPIO_SKL_H_GPP_J21, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_J_21_LAN_SDP_P2_1
+	{GPIO_SKL_H_GPP_J22, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_J_22_LAN_SDP_P3_0
+	{GPIO_SKL_H_GPP_J23, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_J_23_LAN_SDP_P3_1
+
+	{GPIO_SKL_H_GPP_K0, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_K_0_LAN_NCSI_CLK_IN
+	{GPIO_SKL_H_GPP_K1, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_K_1_LAN_NCSI_TXD0
+	{GPIO_SKL_H_GPP_K2, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_K_2_LAN_NCSI_TXD1
+	{GPIO_SKL_H_GPP_K3, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_K_3_LAN_NCSI_TX_EN
+	{GPIO_SKL_H_GPP_K4, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_K_4_LAN_NCSI_CRS_DV
+	{GPIO_SKL_H_GPP_K5, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_K_5_LAN_NCSI_RXD0
+	{GPIO_SKL_H_GPP_K6, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_K_6_LAN_NCSI_RXD1
+	{GPIO_SKL_H_GPP_K7, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_K_7
+	{GPIO_SKL_H_GPP_K8, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,  GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_K_8_LAN_NCSI_ARB_IN
+	{GPIO_SKL_H_GPP_K9, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_K_9_LAN_NCSI_ARB_OUT
+	{GPIO_SKL_H_GPP_K10, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_K_10_PE_RST_N
+
+	{GPIO_SKL_H_GPP_L2, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_L_2_TESTCH0_D0
+	{GPIO_SKL_H_GPP_L3, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_L_3_TESTCH0_D1
+	{GPIO_SKL_H_GPP_L4, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_L_4_TESTCH0_D2
+	{GPIO_SKL_H_GPP_L5, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_L_5_TESTCH0_D3
+	{GPIO_SKL_H_GPP_L6, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_L_6_TESTCH0_D4
+	{GPIO_SKL_H_GPP_L7, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_L_7_TESTCH0_D5
+	{GPIO_SKL_H_GPP_L8, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_L_8_TESTCH0_D6
+	{GPIO_SKL_H_GPP_L9, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_L_9_TESTCH0_D7
+	{GPIO_SKL_H_GPP_L10, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_L_10_TESTCH0_CLK
+	{GPIO_SKL_H_GPP_L11, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_L_11_TESTCH1_D0
+	{GPIO_SKL_H_GPP_L12, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_L_12_TESTCH1_D1
+	{GPIO_SKL_H_GPP_L13, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_L_13_TESTCH1_D2
+	{GPIO_SKL_H_GPP_L14, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_L_14_TESTCH1_D3
+	{GPIO_SKL_H_GPP_L15, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_L_15_TESTCH1_D4
+	{GPIO_SKL_H_GPP_L16, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_L_16_TESTCH1_D5
+	{GPIO_SKL_H_GPP_L17, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_L_17_TESTCH1_D6
+	{GPIO_SKL_H_GPP_L18, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_L_18_TESTCH1_D7
+	{GPIO_SKL_H_GPP_L19, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_L_19_TESTCH1_CLK
+
+	{GPIO_SKL_H_GPD0,	{} }, //GPD_0, controlled by ME
+	{GPIO_SKL_H_GPD1,	{
+		GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock
+		} }, //GPD_1_ACPRESENT
+	{GPIO_SKL_H_GPD2,	{
+		GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutLow,
+		GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock
+		} }, //GPD_2_GBE_WAKE_N
+	{GPIO_SKL_H_GPD3,	{
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock
+		} }, //GPD_3_PWRBTNB_N
+	{GPIO_SKL_H_GPD4,	{
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock
+		} }, //GPD_4_SLP_S3B
+	{GPIO_SKL_H_GPD5,	{
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock
+		} }, //GPD_5_SLP_S4B
+	{GPIO_SKL_H_GPD6,	{
+		GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock
+		} }, //GPD_6_SLPA_N
+	{GPIO_SKL_H_GPD7,	{
+		GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutLow,
+		GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock
+		} }, //GPD_7
+	{GPIO_SKL_H_GPD8,	{
+		GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock
+		} }, //GPD_8_CLK_33K_PCH_SUSCLK_PLD
+	{GPIO_SKL_H_GPD9,	{
+		GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutLow,
+		GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock
+		} }, //GPD_9
+	{GPIO_SKL_H_GPD10, {
+		GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock
+		} }, //GPD_10_FM_SLPS5_N
+	{GPIO_SKL_H_GPD11, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutLow,
+		GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock
+		} }, //GPD_11_GBEPHY
+};
+
+#endif /* _SKXSP_TP_GPIO_H_ */
diff --git a/src/mainboard/ocp/tiogapass/skxsp_tp_iio.h b/src/mainboard/ocp/tiogapass/skxsp_tp_iio.h
new file mode 100644
index 0000000000..0ad92f2fd8
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/skxsp_tp_iio.h
@@ -0,0 +1,101 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 - 2020 Intel Corporation.
+ * Copyright (C) 2019 - 2020 Facebook Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SKXSP_TP_IIO_H_
+#define _SKXSP_TP_IIO_H_
+
+#include <FspmUpd.h>
+#include <soc/pci_devs.h>
+
+/*
+ * Standard Tioga Pass Iio Bifurcation Table
+ * This is SS 2x16 config. As documented in OCP TP spec, there are
+ * 3 configs. SS 2x16 is the most common.
+ * TODO: figure out config through board SKU ID and through PCIe
+ * config GPIO setting (SLT_CFG0 / SLT_CFG1).
+ */
+static const UPD_IIO_BIFURCATION_DATA_ENTRY tp_iio_bifur_table[] = {
+	{ Iio_Socket0, Iio_Iou0, IIO_BIFURCATE_xxxxxx16 }, /* 1A x16 */
+	{ Iio_Socket0, Iio_Iou1, IIO_BIFURCATE_xxxxxx16 }, /* 2A x16 */
+	{ Iio_Socket0, Iio_Iou2, IIO_BIFURCATE_xxxxxx16 }, /* 3A x16 */
+	{ Iio_Socket0, Iio_Mcp0, IIO_BIFURCATE_xxxxxxxx }, /* No MCP */
+	{ Iio_Socket0, Iio_Mcp1, IIO_BIFURCATE_xxxxxxxx }, /* No MCP */
+	{ Iio_Socket1, Iio_Iou0, IIO_BIFURCATE_xxxxxxxx }, /* no IOU0 */
+	{ Iio_Socket1, Iio_Iou1, IIO_BIFURCATE_xxxxxxxx }, /* no IOU1 */
+	{ Iio_Socket1, Iio_Iou2, IIO_BIFURCATE_xxx8xxx8 }, /* 3A x8, 3C x8 */
+	{ Iio_Socket1, Iio_Mcp0, IIO_BIFURCATE_xxxxxxxx }, /* No MCP */
+	{ Iio_Socket1, Iio_Mcp1, IIO_BIFURCATE_xxxxxxxx }, /* No MCP */
+};
+
+/*
+ * Standard Tioga Pass Iio PCIe Port Table
+ */
+static const UPD_PCI_PORT_CONFIG tp_iio_pci_port_skt0[] = {
+	// PortIndex |  HidePort  | DeEmphasis | PortLinkSpeed | MaxPayload |
+	// DfxDnTxPreset | DfxRxPreset | DfxUpTxPreset | Sris | PcieCommonClock | NtbPpd |
+	// NtbSplitBar | NtbBarSizePBar23 | NtbBarSizePBar4 | NtbBarSizePBar5 |
+	// NtbBarSizePBar45 | NtbBarSizeSBar23 | NtbBarSizeSBar4 | NtbBarSizeSbar5 |
+	// NtbBarSizeSBar45 | NtbSBar01Prefetch | NtbXlinkCtlOverride
+	{ PORT_1A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
+		NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
+		0x16, 0x00, 0x03 },
+	{ PORT_1B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
+		NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
+		0x16, 0x00, 0x03 },
+	{ PORT_1C, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
+		NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
+		0x16, 0x00, 0x03 },
+	{ PORT_1D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
+		NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
+		0x16, 0x00, 0x03 },
+	{ PORT_2A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
+		NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
+		0x16, 0x00, 0x03 },
+	{ PORT_2B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
+		NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
+		0x16, 0x00, 0x03 },
+	{ PORT_2C, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
+		NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
+		0x16, 0x00, 0x03 },
+	{ PORT_2D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
+		NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
+		0x16, 0x00, 0x03 },
+	{ PORT_3A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
+		NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
+		0x16, 0x00, 0x03 },
+	{ PORT_3B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
+		NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
+		0x16, 0x00, 0x03 },
+	{ PORT_3C, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
+		NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
+		0x16, 0x00, 0x03 },
+	{ PORT_3D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
+		NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
+		0x16, 0x00, 0x03 },
+};
+
+/*
+ * Standard Tioga Pass PCH PCIe Port Table
+ */
+static const UPD_PCH_PCIE_PORT tp_pch_pci_port_skt0[] = {
+	//PortIndex ; ForceEnable ; PortLinkSpeed
+	{ 0x00, 0x00, PcieAuto },
+	{ 0x04, 0x00, PcieAuto },
+	{ 0x05, 0x00, PcieAuto },
+};
+
+#endif /* _SKXSP_TP_IIO_H_ */