diff --git a/src/arch/arm/include/arch/hlt.h b/src/arch/arm/include/arch/hlt.h
index a6a67576fd..fd2aac9c9f 100644
--- a/src/arch/arm/include/arch/hlt.h
+++ b/src/arch/arm/include/arch/hlt.h
@@ -14,7 +14,9 @@
 #ifndef ARCH_HLT_H
 #define ARCH_HLT_H
 
-static inline __attribute__((always_inline)) void hlt(void)
+#include <compiler.h>
+
+static __always_inline void hlt(void)
 {
 	for (;;) ;
 }
diff --git a/src/arch/arm/include/smp/spinlock.h b/src/arch/arm/include/smp/spinlock.h
index f98900a66b..189bf2c507 100644
--- a/src/arch/arm/include/smp/spinlock.h
+++ b/src/arch/arm/include/smp/spinlock.h
@@ -33,7 +33,7 @@ typedef struct {
 #define spin_is_locked(x)	(*(volatile char *)(&(x)->lock) != 0)
 #define spin_unlock_wait(x)	do { barrier(); } while (spin_is_locked(x))
 
-static inline __attribute__((always_inline)) void spin_lock(spinlock_t *lock)
+static __always_inline void spin_lock(spinlock_t *lock)
 {
 	unsigned long tmp;
 	__asm__ __volatile__ (
@@ -49,7 +49,7 @@ static inline __attribute__((always_inline)) void spin_lock(spinlock_t *lock)
 	barrier();
 }
 
-static inline __attribute__((always_inline)) void spin_unlock(spinlock_t *lock)
+static __always_inline void spin_unlock(spinlock_t *lock)
 {
 	__asm__ __volatile__(
 		"	str	%1, [%0]\n"
diff --git a/src/arch/arm64/include/arch/hlt.h b/src/arch/arm64/include/arch/hlt.h
index a6a67576fd..fd2aac9c9f 100644
--- a/src/arch/arm64/include/arch/hlt.h
+++ b/src/arch/arm64/include/arch/hlt.h
@@ -14,7 +14,9 @@
 #ifndef ARCH_HLT_H
 #define ARCH_HLT_H
 
-static inline __attribute__((always_inline)) void hlt(void)
+#include <compiler.h>
+
+static __always_inline void hlt(void)
 {
 	for (;;) ;
 }
diff --git a/src/arch/mips/include/arch/hlt.h b/src/arch/mips/include/arch/hlt.h
index b99376f2f5..dd66c440ab 100644
--- a/src/arch/mips/include/arch/hlt.h
+++ b/src/arch/mips/include/arch/hlt.h
@@ -16,7 +16,9 @@
 #ifndef __MIPS_ARCH_HLT_H
 #define __MIPS_ARCH_HLT_H
 
-static inline __attribute__((always_inline)) void hlt(void)
+#include <compiler.h>
+
+static inline __always_inline void hlt(void)
 {
 	for (;;)
 		;
diff --git a/src/arch/power8/include/arch/hlt.h b/src/arch/power8/include/arch/hlt.h
index 0fa910b6b0..19c7ecceb8 100644
--- a/src/arch/power8/include/arch/hlt.h
+++ b/src/arch/power8/include/arch/hlt.h
@@ -11,7 +11,9 @@
  * GNU General Public License for more details.
  */
 
-static inline __attribute__((always_inline)) void hlt(void)
+#include <compiler.h>
+
+static __always_inline void hlt(void)
 {
 	while (1)
 		;
diff --git a/src/arch/riscv/include/arch/hlt.h b/src/arch/riscv/include/arch/hlt.h
index da0277821b..2ea2e01f50 100644
--- a/src/arch/riscv/include/arch/hlt.h
+++ b/src/arch/riscv/include/arch/hlt.h
@@ -11,7 +11,9 @@
  * GNU General Public License for more details.
  */
 
-static inline __attribute__((always_inline)) void hlt(void)
+#include <compiler.h>
+
+static __always_inline void hlt(void)
 {
 	while (1);
 }
diff --git a/src/arch/riscv/include/arch/io.h b/src/arch/riscv/include/arch/io.h
index a19f4b5334..9f672f9505 100644
--- a/src/arch/riscv/include/arch/io.h
+++ b/src/arch/riscv/include/arch/io.h
@@ -15,33 +15,34 @@
 #define _ASM_IO_H
 
 #include <stdint.h>
+#include <compiler.h>
 
-static inline __attribute__((always_inline)) uint8_t read8(const volatile void *addr)
+static __always_inline uint8_t read8(const volatile void *addr)
 {
 	return *((volatile uint8_t *)(addr));
 }
 
-static inline __attribute__((always_inline)) uint16_t read16(const volatile void *addr)
+static __always_inline uint16_t read16(const volatile void *addr)
 {
 	return *((volatile uint16_t *)(addr));
 }
 
-static inline __attribute__((always_inline)) uint32_t read32(const volatile void *addr)
+static __always_inline uint32_t read32(const volatile void *addr)
 {
 	return *((volatile uint32_t *)(addr));
 }
 
-static inline __attribute__((always_inline)) void write8(volatile void *addr, uint8_t value)
+static __always_inline void write8(volatile void *addr, uint8_t value)
 {
 	*((volatile uint8_t *)(addr)) = value;
 }
 
-static inline __attribute__((always_inline)) void write16(volatile void *addr, uint16_t value)
+static __always_inline void write16(volatile void *addr, uint16_t value)
 {
 	*((volatile uint16_t *)(addr)) = value;
 }
 
-static inline __attribute__((always_inline)) void write32(volatile void *addr, uint32_t value)
+static __always_inline void write32(volatile void *addr, uint32_t value)
 {
 	*((volatile uint32_t *)(addr)) = value;
 }
diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h
index 5f11c9dc0c..99d10004db 100644
--- a/src/arch/x86/include/arch/cpu.h
+++ b/src/arch/x86/include/arch/cpu.h
@@ -242,7 +242,6 @@ static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms)
 #endif
 
 #define asmlinkage __attribute__((regparm(0)))
-#define alwaysinline inline __attribute__((always_inline))
 
 #ifndef __ROMCC__
 /*
diff --git a/src/arch/x86/include/arch/hlt.h b/src/arch/x86/include/arch/hlt.h
index 0394ce830d..cf7176ae90 100644
--- a/src/arch/x86/include/arch/hlt.h
+++ b/src/arch/x86/include/arch/hlt.h
@@ -20,7 +20,9 @@ static void hlt(void)
 	__builtin_hlt();
 }
 #else
-static inline __attribute__((always_inline)) void hlt(void)
+#include <compiler.h>
+
+static __always_inline void hlt(void)
 {
 	asm("hlt");
 }
diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h
index 37b2e957fe..64b5f120e0 100644
--- a/src/arch/x86/include/arch/io.h
+++ b/src/arch/x86/include/arch/io.h
@@ -14,6 +14,7 @@
 #ifndef _ASM_IO_H
 #define _ASM_IO_H
 
+#include <compiler.h>
 #include <endian.h>
 #include <stdint.h>
 #include <rules.h>
@@ -156,52 +157,52 @@ static inline void insl(uint16_t port, void *addr, unsigned long count)
 		);
 }
 
-static inline __attribute__((always_inline)) uint8_t read8(
+static __always_inline uint8_t read8(
 	const volatile void *addr)
 {
 	return *((volatile uint8_t *)(addr));
 }
 
-static inline __attribute__((always_inline)) uint16_t read16(
+static __always_inline uint16_t read16(
 	const volatile void *addr)
 {
 	return *((volatile uint16_t *)(addr));
 }
 
-static inline __attribute__((always_inline)) uint32_t read32(
+static __always_inline uint32_t read32(
 	const volatile void *addr)
 {
 	return *((volatile uint32_t *)(addr));
 }
 
 #ifndef __ROMCC__
-static inline __attribute__((always_inline)) uint64_t read64(
+static __always_inline uint64_t read64(
 	const volatile void *addr)
 {
 	return *((volatile uint64_t *)(addr));
 }
 #endif
 
-static inline __attribute__((always_inline)) void write8(volatile void *addr,
+static __always_inline void write8(volatile void *addr,
 	uint8_t value)
 {
 	*((volatile uint8_t *)(addr)) = value;
 }
 
-static inline __attribute__((always_inline)) void write16(volatile void *addr,
+static __always_inline void write16(volatile void *addr,
 	uint16_t value)
 {
 	*((volatile uint16_t *)(addr)) = value;
 }
 
-static inline __attribute__((always_inline)) void write32(volatile void *addr,
+static __always_inline void write32(volatile void *addr,
 	uint32_t value)
 {
 	*((volatile uint32_t *)(addr)) = value;
 }
 
 #ifndef __ROMCC__
-static inline __attribute__((always_inline)) void write64(volatile void *addr,
+static __always_inline void write64(volatile void *addr,
 	uint64_t value)
 {
 	*((volatile uint64_t *)(addr)) = value;
@@ -268,7 +269,7 @@ typedef u32 device_t;
 #include <arch/pci_io_cfg.h>
 #include <arch/pci_mmio_cfg.h>
 
-static inline __attribute__((always_inline))
+static __always_inline
 uint8_t pci_read_config8(pci_devfn_t dev, unsigned int where)
 {
 	if (IS_ENABLED(CONFIG_MMCONF_SUPPORT))
@@ -277,7 +278,7 @@ uint8_t pci_read_config8(pci_devfn_t dev, unsigned int where)
 		return pci_io_read_config8(dev, where);
 }
 
-static inline __attribute__((always_inline))
+static __always_inline
 uint16_t pci_read_config16(pci_devfn_t dev, unsigned int where)
 {
 	if (IS_ENABLED(CONFIG_MMCONF_SUPPORT))
@@ -286,7 +287,7 @@ uint16_t pci_read_config16(pci_devfn_t dev, unsigned int where)
 		return pci_io_read_config16(dev, where);
 }
 
-static inline __attribute__((always_inline))
+static __always_inline
 uint32_t pci_read_config32(pci_devfn_t dev, unsigned int where)
 {
 	if (IS_ENABLED(CONFIG_MMCONF_SUPPORT))
@@ -295,7 +296,7 @@ uint32_t pci_read_config32(pci_devfn_t dev, unsigned int where)
 		return pci_io_read_config32(dev, where);
 }
 
-static inline __attribute__((always_inline))
+static __always_inline
 void pci_write_config8(pci_devfn_t dev, unsigned int where, uint8_t value)
 {
 	if (IS_ENABLED(CONFIG_MMCONF_SUPPORT))
@@ -304,7 +305,7 @@ void pci_write_config8(pci_devfn_t dev, unsigned int where, uint8_t value)
 		pci_io_write_config8(dev, where, value);
 }
 
-static inline __attribute__((always_inline))
+static __always_inline
 void pci_write_config16(pci_devfn_t dev, unsigned int where, uint16_t value)
 {
 	if (IS_ENABLED(CONFIG_MMCONF_SUPPORT))
@@ -313,7 +314,7 @@ void pci_write_config16(pci_devfn_t dev, unsigned int where, uint16_t value)
 		pci_io_write_config16(dev, where, value);
 }
 
-static inline __attribute__((always_inline))
+static __always_inline
 void pci_write_config32(pci_devfn_t dev, unsigned int where, uint32_t value)
 {
 	if (IS_ENABLED(CONFIG_MMCONF_SUPPORT))
@@ -365,7 +366,7 @@ static inline pci_devfn_t pci_locate_device_on_bus(unsigned int pci_id,
 }
 
 /* Generic functions for pnp devices */
-static inline __attribute__((always_inline)) void pnp_write_config(
+static __always_inline void pnp_write_config(
 	pnp_devfn_t dev, uint8_t reg, uint8_t value)
 {
 	unsigned int port = dev >> 8;
@@ -373,7 +374,7 @@ static inline __attribute__((always_inline)) void pnp_write_config(
 	outb(value, port + 1);
 }
 
-static inline __attribute__((always_inline)) uint8_t pnp_read_config(
+static __always_inline uint8_t pnp_read_config(
 	pnp_devfn_t dev, uint8_t reg)
 {
 	unsigned int port = dev >> 8;
@@ -381,46 +382,46 @@ static inline __attribute__((always_inline)) uint8_t pnp_read_config(
 	return inb(port + 1);
 }
 
-static inline __attribute__((always_inline))
+static __always_inline
 void pnp_set_logical_device(pnp_devfn_t dev)
 {
 	unsigned int device = dev & 0xff;
 	pnp_write_config(dev, 0x07, device);
 }
 
-static inline __attribute__((always_inline))
+static __always_inline
 void pnp_set_enable(pnp_devfn_t dev, int enable)
 {
 	pnp_write_config(dev, 0x30, enable?0x1:0x0);
 }
 
-static inline __attribute__((always_inline))
+static __always_inline
 int pnp_read_enable(pnp_devfn_t dev)
 {
 	return !!pnp_read_config(dev, 0x30);
 }
 
-static inline __attribute__((always_inline))
+static __always_inline
 void pnp_set_iobase(pnp_devfn_t dev, unsigned int index, unsigned int iobase)
 {
 	pnp_write_config(dev, index + 0, (iobase >> 8) & 0xff);
 	pnp_write_config(dev, index + 1, iobase & 0xff);
 }
 
-static inline __attribute__((always_inline))
+static __always_inline
 uint16_t pnp_read_iobase(pnp_devfn_t dev, unsigned int index)
 {
 	return ((uint16_t)(pnp_read_config(dev, index)) << 8)
 		| pnp_read_config(dev, index + 1);
 }
 
-static inline __attribute__((always_inline))
+static __always_inline
 void pnp_set_irq(pnp_devfn_t dev, unsigned int index, unsigned int irq)
 {
 	pnp_write_config(dev, index, irq);
 }
 
-static inline __attribute__((always_inline))
+static __always_inline
 void pnp_set_drq(pnp_devfn_t dev, unsigned int index, unsigned int drq)
 {
 	pnp_write_config(dev, index, drq & 0xff);
diff --git a/src/arch/x86/include/arch/pci_io_cfg.h b/src/arch/x86/include/arch/pci_io_cfg.h
index a09b488032..15d1a132cf 100644
--- a/src/arch/x86/include/arch/pci_io_cfg.h
+++ b/src/arch/x86/include/arch/pci_io_cfg.h
@@ -14,9 +14,10 @@
 #ifndef _PCI_IO_CFG_H
 #define _PCI_IO_CFG_H
 
+#include <compiler.h>
 #include <arch/io.h>
 
-static inline __attribute__((always_inline))
+static __always_inline
 unsigned int pci_io_encode_addr(pci_devfn_t dev, unsigned int where)
 {
 	if (IS_ENABLED(CONFIG_PCI_IO_CFG_EXT)) {
@@ -27,7 +28,7 @@ unsigned int pci_io_encode_addr(pci_devfn_t dev, unsigned int where)
 	}
 }
 
-static inline __attribute__((always_inline))
+static __always_inline
 uint8_t pci_io_read_config8(pci_devfn_t dev, unsigned int where)
 {
 	unsigned int addr = pci_io_encode_addr(dev, where);
@@ -35,7 +36,7 @@ uint8_t pci_io_read_config8(pci_devfn_t dev, unsigned int where)
 	return inb(0xCFC + (addr & 3));
 }
 
-static inline __attribute__((always_inline))
+static __always_inline
 uint16_t pci_io_read_config16(pci_devfn_t dev, unsigned int where)
 {
 	unsigned int addr = pci_io_encode_addr(dev, where);
@@ -43,7 +44,7 @@ uint16_t pci_io_read_config16(pci_devfn_t dev, unsigned int where)
 	return inw(0xCFC + (addr & 2));
 }
 
-static inline __attribute__((always_inline))
+static __always_inline
 uint32_t pci_io_read_config32(pci_devfn_t dev, unsigned int where)
 {
 	unsigned int addr = pci_io_encode_addr(dev, where);
@@ -51,7 +52,7 @@ uint32_t pci_io_read_config32(pci_devfn_t dev, unsigned int where)
 	return inl(0xCFC);
 }
 
-static inline __attribute__((always_inline))
+static __always_inline
 void pci_io_write_config8(pci_devfn_t dev, unsigned int where, uint8_t value)
 {
 	unsigned int addr = pci_io_encode_addr(dev, where);
@@ -59,7 +60,7 @@ void pci_io_write_config8(pci_devfn_t dev, unsigned int where, uint8_t value)
 	outb(value, 0xCFC + (addr & 3));
 }
 
-static inline __attribute__((always_inline))
+static __always_inline
 void pci_io_write_config16(pci_devfn_t dev, unsigned int where, uint16_t value)
 {
 	unsigned int addr = pci_io_encode_addr(dev, where);
@@ -67,7 +68,7 @@ void pci_io_write_config16(pci_devfn_t dev, unsigned int where, uint16_t value)
 	outw(value, 0xCFC + (addr & 2));
 }
 
-static inline __attribute__((always_inline))
+static __always_inline
 void pci_io_write_config32(pci_devfn_t dev, unsigned int where, uint32_t value)
 {
 	unsigned int addr = pci_io_encode_addr(dev, where);
diff --git a/src/arch/x86/include/arch/pci_mmio_cfg.h b/src/arch/x86/include/arch/pci_mmio_cfg.h
index efd8269ad2..a5ca574466 100644
--- a/src/arch/x86/include/arch/pci_mmio_cfg.h
+++ b/src/arch/x86/include/arch/pci_mmio_cfg.h
@@ -17,10 +17,11 @@
 #define _PCI_MMIO_CFG_H
 
 #include <arch/io.h>
+#include <compiler.h>
 
 #define DEFAULT_PCIEXBAR	CONFIG_MMCONF_BASE_ADDRESS
 
-static inline __attribute__((always_inline))
+static __always_inline
 u8 pci_mmio_read_config8(pci_devfn_t dev, unsigned int where)
 {
 	void *addr;
@@ -28,7 +29,7 @@ u8 pci_mmio_read_config8(pci_devfn_t dev, unsigned int where)
 	return read8(addr);
 }
 
-static inline __attribute__((always_inline))
+static __always_inline
 u16 pci_mmio_read_config16(pci_devfn_t dev, unsigned int where)
 {
 	void *addr;
@@ -36,7 +37,7 @@ u16 pci_mmio_read_config16(pci_devfn_t dev, unsigned int where)
 	return read16(addr);
 }
 
-static inline __attribute__((always_inline))
+static __always_inline
 u32 pci_mmio_read_config32(pci_devfn_t dev, unsigned int where)
 {
 	void *addr;
@@ -44,7 +45,7 @@ u32 pci_mmio_read_config32(pci_devfn_t dev, unsigned int where)
 	return read32(addr);
 }
 
-static inline __attribute__((always_inline))
+static __always_inline
 void pci_mmio_write_config8(pci_devfn_t dev, unsigned int where, u8 value)
 {
 	void *addr;
@@ -52,7 +53,7 @@ void pci_mmio_write_config8(pci_devfn_t dev, unsigned int where, u8 value)
 	write8(addr, value);
 }
 
-static inline __attribute__((always_inline))
+static __always_inline
 void pci_mmio_write_config16(pci_devfn_t dev, unsigned int where, u16 value)
 {
 	void *addr;
@@ -60,7 +61,7 @@ void pci_mmio_write_config16(pci_devfn_t dev, unsigned int where, u16 value)
 	write16(addr, value);
 }
 
-static inline __attribute__((always_inline))
+static __always_inline
 void pci_mmio_write_config32(pci_devfn_t dev, unsigned int where, u32 value)
 {
 	void *addr;
diff --git a/src/arch/x86/include/arch/smp/atomic.h b/src/arch/x86/include/arch/smp/atomic.h
index 1ca165edae..b12da12e54 100644
--- a/src/arch/x86/include/arch/smp/atomic.h
+++ b/src/arch/x86/include/arch/smp/atomic.h
@@ -14,6 +14,8 @@
 #ifndef ARCH_SMP_ATOMIC_H
 #define ARCH_SMP_ATOMIC_H
 
+#include <compiler.h>
+
 /*
  * Make sure gcc doesn't try to be clever and move things around
  * on us. We need to use _exactly_ the address the user gave us,
@@ -55,7 +57,7 @@ typedef struct { volatile int counter; } atomic_t;
  * Atomically increments v by 1.  Note that the guaranteed
  * useful range of an atomic_t is only 24 bits.
  */
-static inline __attribute__((always_inline)) void atomic_inc(atomic_t *v)
+static __always_inline void atomic_inc(atomic_t *v)
 {
 	__asm__ __volatile__(
 		"lock ; incl %0"
@@ -70,7 +72,7 @@ static inline __attribute__((always_inline)) void atomic_inc(atomic_t *v)
  * Atomically decrements v by 1.  Note that the guaranteed
  * useful range of an atomic_t is only 24 bits.
  */
-static inline __attribute__((always_inline)) void atomic_dec(atomic_t *v)
+static __always_inline void atomic_dec(atomic_t *v)
 {
 	__asm__ __volatile__(
 		"lock ; decl %0"
diff --git a/src/arch/x86/include/arch/smp/spinlock.h b/src/arch/x86/include/arch/smp/spinlock.h
index 1c1def1252..212cd8cd64 100644
--- a/src/arch/x86/include/arch/smp/spinlock.h
+++ b/src/arch/x86/include/arch/smp/spinlock.h
@@ -14,6 +14,8 @@
 #ifndef ARCH_SMP_SPINLOCK_H
 #define ARCH_SMP_SPINLOCK_H
 
+#include <compiler.h>
+
 #if !defined(__PRE_RAM__) \
 	|| IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK)	\
 	|| IS_ENABLED(CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK)	\
@@ -73,14 +75,14 @@ void initialize_romstage_microcode_cbfs_lock(void);
 #define spin_unlock_string \
 	"movb $1,%0"
 
-static inline __attribute__((always_inline)) void spin_lock(spinlock_t *lock)
+static __always_inline void spin_lock(spinlock_t *lock)
 {
 	__asm__ __volatile__(
 		spin_lock_string
 		: "=m" (lock->lock) : : "memory");
 }
 
-static inline __attribute__((always_inline)) void spin_unlock(spinlock_t *lock)
+static __always_inline void spin_unlock(spinlock_t *lock)
 {
 	__asm__ __volatile__(
 		spin_unlock_string
@@ -88,7 +90,7 @@ static inline __attribute__((always_inline)) void spin_unlock(spinlock_t *lock)
 }
 
 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
-static inline __attribute__((always_inline)) void cpu_relax(void)
+static __always_inline void cpu_relax(void)
 {
 	__asm__ __volatile__("rep;nop" : : : "memory");
 }
diff --git a/src/commonlib/lz4_wrapper.c b/src/commonlib/lz4_wrapper.c
index 4050ac9bb3..8f516089ca 100644
--- a/src/commonlib/lz4_wrapper.c
+++ b/src/commonlib/lz4_wrapper.c
@@ -84,7 +84,7 @@ typedef uint32_t U32;
 typedef  int32_t S32;
 typedef uint64_t U64;
 
-#define FORCE_INLINE static inline __attribute__((always_inline))
+#define FORCE_INLINE static __always_inline
 #define likely(expr) __builtin_expect((expr) != 0, 1)
 #define unlikely(expr) __builtin_expect((expr) != 0, 0)
 
diff --git a/src/cpu/amd/car/disable_cache_as_ram.c b/src/cpu/amd/car/disable_cache_as_ram.c
index af5a2e985d..36d4120453 100644
--- a/src/cpu/amd/car/disable_cache_as_ram.c
+++ b/src/cpu/amd/car/disable_cache_as_ram.c
@@ -19,10 +19,11 @@
  * WARNING: this file will be used by both any AP cores and core 0 / node 0
  */
 
+#include <compiler.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/msr.h>
 
-static inline __attribute__((always_inline)) uint32_t amd_fam1x_cpu_family(void)
+static __always_inline uint32_t amd_fam1x_cpu_family(void)
 {
 	uint32_t family;
 
@@ -32,7 +33,7 @@ static inline __attribute__((always_inline)) uint32_t amd_fam1x_cpu_family(void)
 	return family;
 }
 
-static inline __attribute__((always_inline))
+static __always_inline
 void disable_cache_as_ram_real(uint8_t skip_sharedc_config)
 {
 	msr_t msr;
diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c
index f1a607b6ea..4911eca38a 100644
--- a/src/cpu/amd/family_10h-family_15h/init_cpus.c
+++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c
@@ -14,6 +14,7 @@
  * GNU General Public License for more details.
  */
 
+#include <compiler.h>
 #include "init_cpus.h"
 
 #if IS_ENABLED(CONFIG_HAVE_OPTION_TABLE)
@@ -231,7 +232,7 @@ static inline int lapic_remote_read(int apicid, int reg, u32 *pvalue)
 static void init_fidvid_ap(u32 apicid, u32 nodeid, u32 coreid);
 #endif
 
-static inline __attribute__((always_inline))
+static __always_inline
 void print_apicid_nodeid_coreid(u32 apicid, struct node_core_id id,
 				const char *str)
 {
diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c
index d888e4410b..99a62896de 100644
--- a/src/cpu/x86/smm/smihandler.c
+++ b/src/cpu/x86/smm/smihandler.c
@@ -60,7 +60,7 @@ void smi_release_lock(void)
 }
 
 #define LAPIC_ID 0xfee00020
-static inline __attribute__((always_inline)) unsigned long nodeid(void)
+static __always_inline unsigned long nodeid(void)
 {
 	return (*((volatile unsigned long *)(LAPIC_ID)) >> 24);
 }
diff --git a/src/include/compiler.h b/src/include/compiler.h
index 4df1cab7e6..96c2045e4d 100644
--- a/src/include/compiler.h
+++ b/src/include/compiler.h
@@ -27,5 +27,6 @@
 #define __must_check __attribute__((warn_unused_result))
 #define __weak __attribute__((weak))
 #define __noreturn __attribute__((noreturn))
+#define __always_inline inline __attribute__((always_inline))
 
 #endif
diff --git a/src/include/cpu/amd/mtrr.h b/src/include/cpu/amd/mtrr.h
index b31648d0af..9661b636cc 100644
--- a/src/include/cpu/amd/mtrr.h
+++ b/src/include/cpu/amd/mtrr.h
@@ -38,13 +38,14 @@
 
 #if !defined(__PRE_RAM__) && !defined(__ASSEMBLER__)
 
+#include <compiler.h>
 #include <cpu/x86/msr.h>
 
 void amd_setup_mtrrs(void);
 struct device;
 void add_uma_resource_below_tolm(struct device *nb, int idx);
 
-static inline __attribute__((always_inline)) msr_t rdmsr_amd(unsigned int index)
+static __always_inline msr_t rdmsr_amd(unsigned int index)
 {
 	msr_t result;
 	__asm__ __volatile__ (
@@ -55,8 +56,7 @@ static inline __attribute__((always_inline)) msr_t rdmsr_amd(unsigned int index)
 	return result;
 }
 
-static inline __attribute__((always_inline)) void wrmsr_amd(unsigned int index,
-	msr_t msr)
+static __always_inline void wrmsr_amd(unsigned int index, msr_t msr)
 {
 	__asm__ __volatile__ (
 		"wrmsr"
diff --git a/src/include/cpu/x86/cache.h b/src/include/cpu/x86/cache.h
index e0a335971b..81d2ae7223 100644
--- a/src/include/cpu/x86/cache.h
+++ b/src/include/cpu/x86/cache.h
@@ -16,6 +16,7 @@
 #ifndef CPU_X86_CACHE
 #define CPU_X86_CACHE
 
+#include <compiler.h>
 #include <cpu/x86/cr.h>
 
 #define CR0_CacheDisable	(CR0_CD)
@@ -55,7 +56,7 @@ static inline void clflush(void *addr)
 	asm volatile ("clflush (%0)"::"r" (addr));
 }
 
-/* The following functions require the always_inline due to AMD
+/* The following functions require the __always_inline due to AMD
  * function STOP_CAR_AND_CPU that disables cache as
  * RAM, the cache as RAM stack can no longer be used. Called
  * functions must be inlined to avoid stack usage. Also, the
@@ -63,9 +64,9 @@ static inline void clflush(void *addr)
  * allocated them from the stack. With gcc 4.5.0, some functions
  * declared as inline are not being inlined. This patch forces
  * these functions to always be inlined by adding the qualifier
- * __attribute__((always_inline)) to their declaration.
+ * __always_inline to their declaration.
  */
-static inline __attribute__((always_inline)) void enable_cache(void)
+static __always_inline void enable_cache(void)
 {
 	unsigned long cr0;
 	cr0 = read_cr0();
@@ -73,7 +74,7 @@ static inline __attribute__((always_inline)) void enable_cache(void)
 	write_cr0(cr0);
 }
 
-static inline __attribute__((always_inline)) void disable_cache(void)
+static __always_inline void disable_cache(void)
 {
 	/* Disable and write back the cache */
 	unsigned long cr0;
diff --git a/src/include/cpu/x86/cr.h b/src/include/cpu/x86/cr.h
index 5183c77f89..229a67d422 100644
--- a/src/include/cpu/x86/cr.h
+++ b/src/include/cpu/x86/cr.h
@@ -18,6 +18,7 @@
 
 #if !defined(__ASSEMBLER__)
 
+#include <compiler.h>
 #include <stdint.h>
 #include <arch/cpu.h>
 
@@ -37,7 +38,7 @@
 #define CRx_IN   "r"
 #define CRx_RET  "=r"
 #endif
-static alwaysinline CRx_TYPE read_cr0(void)
+static __always_inline CRx_TYPE read_cr0(void)
 {
 	CRx_TYPE value;
 	__asm__ __volatile__ (
@@ -49,7 +50,7 @@ static alwaysinline CRx_TYPE read_cr0(void)
 	return value;
 }
 
-static alwaysinline void write_cr0(CRx_TYPE data)
+static __always_inline void write_cr0(CRx_TYPE data)
 {
 	__asm__ __volatile__ (
 		"mov %0, %%cr0"
@@ -59,7 +60,7 @@ static alwaysinline void write_cr0(CRx_TYPE data)
 	);
 }
 
-static alwaysinline CRx_TYPE read_cr2(void)
+static __always_inline CRx_TYPE read_cr2(void)
 {
 	CRx_TYPE value;
 	__asm__ __volatile__ (
@@ -71,7 +72,7 @@ static alwaysinline CRx_TYPE read_cr2(void)
 	return value;
 }
 
-static alwaysinline CRx_TYPE read_cr3(void)
+static __always_inline CRx_TYPE read_cr3(void)
 {
 	CRx_TYPE value;
 	__asm__ __volatile__ (
@@ -83,7 +84,7 @@ static alwaysinline CRx_TYPE read_cr3(void)
 	return value;
 }
 
-static alwaysinline void write_cr3(CRx_TYPE data)
+static __always_inline void write_cr3(CRx_TYPE data)
 {
 	__asm__ __volatile__ (
 		"mov %0, %%cr3"
@@ -92,7 +93,7 @@ static alwaysinline void write_cr3(CRx_TYPE data)
 		: COMPILER_BARRIER
 	);
 }
-static alwaysinline CRx_TYPE read_cr4(void)
+static __always_inline CRx_TYPE read_cr4(void)
 {
 	CRx_TYPE value;
 	__asm__ __volatile__ (
@@ -104,7 +105,7 @@ static alwaysinline CRx_TYPE read_cr4(void)
 	return value;
 }
 
-static alwaysinline void write_cr4(CRx_TYPE data)
+static __always_inline void write_cr4(CRx_TYPE data)
 {
 	__asm__ __volatile__ (
 		"mov %0, %%cr4"
diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h
index 6121230a22..5ac3c5e2e8 100644
--- a/src/include/cpu/x86/lapic.h
+++ b/src/include/cpu/x86/lapic.h
@@ -1,24 +1,23 @@
 #ifndef CPU_X86_LAPIC_H
 #define CPU_X86_LAPIC_H
 
+#include <compiler.h>
 #include <cpu/x86/lapic_def.h>
 #include <cpu/x86/msr.h>
 #include <halt.h>
 #include <smp/node.h>
 
-static inline __attribute__((always_inline)) unsigned long lapic_read(
-	unsigned long reg)
+static __always_inline unsigned long lapic_read(unsigned long reg)
 {
 	return *((volatile unsigned long *)(LAPIC_DEFAULT_BASE+reg));
 }
 
-static inline __attribute__((always_inline)) void lapic_write(unsigned long reg,
-	unsigned long v)
+static __always_inline void lapic_write(unsigned long reg, unsigned long v)
 {
 	*((volatile unsigned long *)(LAPIC_DEFAULT_BASE+reg)) = v;
 }
 
-static inline __attribute__((always_inline)) void lapic_wait_icr_idle(void)
+static __always_inline void lapic_wait_icr_idle(void)
 {
 	do { } while (lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY);
 }
@@ -42,7 +41,7 @@ static inline void disable_lapic(void)
 	wrmsr(LAPIC_BASE_MSR, msr);
 }
 
-static inline __attribute__((always_inline)) unsigned long lapicid(void)
+static __always_inline unsigned long lapicid(void)
 {
 	return lapic_read(LAPIC_ID) >> 24;
 }
@@ -51,7 +50,7 @@ static inline __attribute__((always_inline)) unsigned long lapicid(void)
 /* If we need to go back to sipi wait, we use the long non-inlined version of
  * this function in lapic_cpu_init.c
  */
-static inline __attribute__((always_inline)) void stop_this_cpu(void)
+static __always_inline void stop_this_cpu(void)
 {
 	/* Called by an AP when it is ready to halt and wait for a new task */
 	halt();
diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h
index 74c2521af5..290c54a499 100644
--- a/src/include/cpu/x86/msr.h
+++ b/src/include/cpu/x86/msr.h
@@ -1,6 +1,8 @@
 #ifndef CPU_X86_MSR_H
 #define CPU_X86_MSR_H
 
+#include <compiler.h>
+
 /* Intel SDM: Table 2-1
  * IA-32 architectural MSR: Extended Feature Enable Register
  */
@@ -50,19 +52,18 @@ msr_t soc_msr_read(unsigned int index);
 void soc_msr_write(unsigned int index, msr_t msr);
 
 /* Handle MSR references in the other source code */
-static inline __attribute__((always_inline)) msr_t rdmsr(unsigned int index)
+static __always_inline msr_t rdmsr(unsigned int index)
 {
 	return soc_msr_read(index);
 }
 
-static inline __attribute__((always_inline)) void wrmsr(unsigned int index,
-	msr_t msr)
+static __always_inline void wrmsr(unsigned int index, msr_t msr)
 {
 	soc_msr_write(index, msr);
 }
 #else /* CONFIG_SOC_SETS_MSRS */
 
-/* The following functions require the always_inline due to AMD
+/* The following functions require the __always_inline due to AMD
  * function STOP_CAR_AND_CPU that disables cache as
  * RAM, the cache as RAM stack can no longer be used. Called
  * functions must be inlined to avoid stack usage. Also, the
@@ -70,9 +71,9 @@ static inline __attribute__((always_inline)) void wrmsr(unsigned int index,
  * allocated them from the stack. With gcc 4.5.0, some functions
  * declared as inline are not being inlined. This patch forces
  * these functions to always be inlined by adding the qualifier
- * __attribute__((always_inline)) to their declaration.
+ * __always_inline to their declaration.
  */
-static inline __attribute__((always_inline)) msr_t rdmsr(unsigned int index)
+static __always_inline msr_t rdmsr(unsigned int index)
 {
 	msr_t result;
 	__asm__ __volatile__ (
@@ -83,8 +84,7 @@ static inline __attribute__((always_inline)) msr_t rdmsr(unsigned int index)
 	return result;
 }
 
-static inline __attribute__((always_inline)) void wrmsr(unsigned int index,
-	msr_t msr)
+static __always_inline void wrmsr(unsigned int index, msr_t msr)
 {
 	__asm__ __volatile__ (
 		"wrmsr"
diff --git a/src/include/device/pci_ops.h b/src/include/device/pci_ops.h
index 2518f2002d..9e9baa0d60 100644
--- a/src/include/device/pci_ops.h
+++ b/src/include/device/pci_ops.h
@@ -1,6 +1,7 @@
 #ifndef PCI_OPS_H
 #define PCI_OPS_H
 
+#include <compiler.h>
 #include <stdint.h>
 #include <device/device.h>
 #include <arch/pci_ops.h>
@@ -19,28 +20,28 @@ void pci_write_config32(struct device *dev, unsigned int where, u32 val);
  * Use device_t here as the functions are to be used with either
  * __SIMPLE_DEVICE__ defined or undefined.
  */
-static inline __attribute__((always_inline))
+static __always_inline
 void pci_or_config8(device_t dev, unsigned int where, u8 ormask)
 {
 	u8 value = pci_read_config8(dev, where);
 	pci_write_config8(dev, where, value | ormask);
 }
 
-static inline __attribute__((always_inline))
+static __always_inline
 void pci_or_config16(device_t dev, unsigned int where, u16 ormask)
 {
 	u16 value = pci_read_config16(dev, where);
 	pci_write_config16(dev, where, value | ormask);
 }
 
-static inline __attribute__((always_inline))
+static __always_inline
 void pci_or_config32(device_t dev, unsigned int where, u32 ormask)
 {
 	u32 value = pci_read_config32(dev, where);
 	pci_write_config32(dev, where, value | ormask);
 }
 
-static inline __attribute__((always_inline))
+static __always_inline
 void pci_update_config8(device_t dev, int reg, u8 mask, u8 or)
 {
 	u8 reg8;
@@ -51,7 +52,7 @@ void pci_update_config8(device_t dev, int reg, u8 mask, u8 or)
 	pci_write_config8(dev, reg, reg8);
 }
 
-static inline __attribute__((always_inline))
+static __always_inline
 void pci_update_config16(device_t dev, int reg, u16 mask, u16 or)
 {
 	u16 reg16;
@@ -62,7 +63,7 @@ void pci_update_config16(device_t dev, int reg, u16 mask, u16 or)
 	pci_write_config16(dev, reg, reg16);
 }
 
-static inline __attribute__((always_inline))
+static __always_inline
 void pci_update_config32(device_t dev, int reg, u32 mask, u32 or)
 {
 	u32 reg32;
diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c
index b289efe3e1..4919e65ae5 100644
--- a/src/northbridge/intel/e7505/raminit.c
+++ b/src/northbridge/intel/e7505/raminit.c
@@ -24,6 +24,7 @@
  * Steven James 02/06/2003
  */
 
+#include <compiler.h>
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
@@ -911,7 +912,7 @@ static void configure_e7501_ram_addresses(const struct mem_controller
  *
  * NOTE: All cache and stack is lost during ECC scrub loop.
  */
-static inline void __attribute__((always_inline))
+static __always_inline void
 		initialize_ecc(unsigned long ret_addr, unsigned long ret_addr2)
 {
 	uint16_t scrubbed = pci_read_config16(MCHDEV, MCHCFGNS) & 0x08;
diff --git a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c
index 00dc0f715f..a8b2e69ea0 100644
--- a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c
+++ b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c
@@ -264,8 +264,7 @@ static uint32_t *sysctr_cntfid0_ptr = (void *)(SYSCTR_CTLR_BASE + 0x20);
 
 /* Utility functions. */
 
-static inline void __attribute__((always_inline))
-		   __noreturn halt(void)
+static __always_inline void __noreturn halt(void)
 {
 	for (;;);
 }
diff --git a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c
index 2e8c9bb6b3..108b3b07de 100644
--- a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c
+++ b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c
@@ -428,8 +428,7 @@ enum {
 
 /* Utility functions. */
 
-static inline void __attribute__((always_inline))
-		   __noreturn halt(void)
+static __always_inline void __noreturn halt(void)
 {
 	for (;;);
 }