cbmem: rename vdat to chromeos_acpi
There is a confusingly named section in cbmem called vdat. This section holds a data structure called chromeos_acpi_t, which exposes some system information to the Chrome OS userland utility crossystem. Within the chromeos_acpi_t structure, there is a member called vdat. This (currently) holds a VbSharedDataHeader. Rename the outer vdat to chromeos_acpi to make its purpose clear, and prevent the bizarreness of being able to access vdat->vdat. Additionally, disallow external references to the chromeos_acpi data structure in gnvs.c. BUG=b:112288216 TEST=emerge-eve coreboot, run on eve CQ-DEPEND=CL:1164722 Change-Id: Ia74e58cde21678f24b0bb6c1ca15048677116b2e Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/27888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -200,7 +200,7 @@ struct cb_gpios {
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struct cb_gpio gpios[0];
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struct cb_gpio gpios[0];
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};
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};
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#define CB_TAG_VDAT 0x0015
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#define CB_TAG_CHROMEOS_ACPI 0x0015
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#define CB_TAG_VBNV 0x0019
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#define CB_TAG_VBNV 0x0019
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#define CB_TAG_VBOOT_HANDOFF 0x0020
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#define CB_TAG_VBOOT_HANDOFF 0x0020
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#define CB_TAG_DMA 0x0022
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#define CB_TAG_DMA 0x0022
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@ -97,8 +97,8 @@ struct sysinfo_t {
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void *vboot_handoff;
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void *vboot_handoff;
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u32 vboot_handoff_size;
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u32 vboot_handoff_size;
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void *vdat_addr;
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void *chromeos_acpi_addr;
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u32 vdat_size;
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u32 chromeos_acpi_size;
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#if IS_ENABLED(CONFIG_LP_ARCH_X86)
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#if IS_ENABLED(CONFIG_LP_ARCH_X86)
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int x86_rom_var_mtrr_index;
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int x86_rom_var_mtrr_index;
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@ -106,12 +106,12 @@ static void cb_parse_gpios(unsigned char *ptr, struct sysinfo_t *info)
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info->gpios[i] = gpios->gpios[i];
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info->gpios[i] = gpios->gpios[i];
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}
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}
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static void cb_parse_vdat(unsigned char *ptr, struct sysinfo_t *info)
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static void cb_parse_chromeos_acpi(unsigned char *ptr, struct sysinfo_t *info)
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{
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{
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struct lb_range *vdat = (struct lb_range *) ptr;
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struct lb_range *chromeos_acpi = (struct lb_range *) ptr;
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info->vdat_addr = phys_to_virt(vdat->range_start);
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info->chromeos_acpi_addr = phys_to_virt(chromeos_acpi->range_start);
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info->vdat_size = vdat->range_size;
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info->chromeos_acpi_size = chromeos_acpi->range_size;
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}
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}
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static void cb_parse_mac_addresses(unsigned char *ptr,
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static void cb_parse_mac_addresses(unsigned char *ptr,
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@ -357,8 +357,8 @@ int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
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case CB_TAG_GPIO:
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case CB_TAG_GPIO:
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cb_parse_gpios(ptr, info);
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cb_parse_gpios(ptr, info);
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break;
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break;
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case CB_TAG_VDAT:
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case CB_TAG_CHROMEOS_ACPI:
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cb_parse_vdat(ptr, info);
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cb_parse_chromeos_acpi(ptr, info);
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break;
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break;
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case CB_TAG_VBNV:
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case CB_TAG_VBNV:
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cb_parse_vbnv(ptr, info);
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cb_parse_vbnv(ptr, info);
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@ -367,7 +367,7 @@ static int smbios_write_type0(unsigned long *current, int handle)
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#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
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#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
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/* SMBIOS offsets start at 1 rather than 0 */
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/* SMBIOS offsets start at 1 rather than 0 */
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vboot_data->vbt10 = (u32)t->eos + (version_offset - 1);
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acpi_get_chromeos_acpi()->vbt10 = (u32)t->eos + (version_offset - 1);
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#endif
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#endif
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#endif /* CONFIG_CHROMEOS */
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#endif /* CONFIG_CHROMEOS */
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@ -290,7 +290,7 @@ struct lb_gpios {
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struct lb_gpio gpios[0];
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struct lb_gpio gpios[0];
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};
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};
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#define LB_TAG_VDAT 0x0015
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#define LB_TAG_CHROMEOS_ACPI 0x0015
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#define LB_TAG_VBNV 0x0019
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#define LB_TAG_VBNV 0x0019
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#define LB_TAB_VBOOT_HANDOFF 0x0020
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#define LB_TAB_VBOOT_HANDOFF 0x0020
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#define LB_TAB_DMA 0x0022
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#define LB_TAB_DMA 0x0022
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@ -195,15 +195,16 @@ static void lb_gpios(struct lb_header *header)
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}
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}
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}
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}
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static void lb_vdat(struct lb_header *header)
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static void lb_chromeos_acpi(struct lb_header *header)
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{
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{
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#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
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#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
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struct lb_range *vdat;
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struct lb_range *chromeos_acpi;
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vdat = (struct lb_range *)lb_new_record(header);
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chromeos_acpi = (struct lb_range *)lb_new_record(header);
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vdat->tag = LB_TAG_VDAT;
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chromeos_acpi->tag = LB_TAG_CHROMEOS_ACPI;
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vdat->size = sizeof(*vdat);
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chromeos_acpi->size = sizeof(*chromeos_acpi);
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acpi_get_vdat_info(&vdat->range_start, &vdat->range_size);
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acpi_get_chromeos_acpi_info(&chromeos_acpi->range_start,
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&chromeos_acpi->range_size);
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#endif
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#endif
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}
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}
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@ -546,8 +547,8 @@ static uintptr_t write_coreboot_table(uintptr_t rom_table_end)
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/* Record our GPIO settings (ChromeOS specific) */
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/* Record our GPIO settings (ChromeOS specific) */
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lb_gpios(head);
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lb_gpios(head);
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/* pass along the VDAT buffer address */
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/* pass along the chromeos_acpi_t buffer address */
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lb_vdat(head);
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lb_chromeos_acpi(head);
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/* pass along VBNV offsets in CMOS */
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/* pass along VBNV offsets in CMOS */
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lb_vbnv(head);
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lb_vbnv(head);
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@ -27,40 +27,46 @@
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#include "chromeos.h"
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#include "chromeos.h"
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#include "gnvs.h"
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#include "gnvs.h"
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chromeos_acpi_t *vboot_data = NULL;
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static chromeos_acpi_t *chromeos_acpi;
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static u32 me_hash_saved[8];
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static u32 me_hash_saved[8];
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void chromeos_init_vboot(chromeos_acpi_t *chromeos)
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void chromeos_init_vboot(chromeos_acpi_t *init)
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{
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{
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vboot_data = chromeos;
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chromeos_acpi = init;
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/* Copy saved ME hash into NVS */
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/* Copy saved ME hash into NVS */
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memcpy(vboot_data->mehh, me_hash_saved, sizeof(vboot_data->mehh));
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memcpy(chromeos_acpi->mehh, me_hash_saved, sizeof(chromeos_acpi->mehh));
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struct vboot_handoff *vboot_handoff;
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struct vboot_handoff *vboot_handoff;
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if (vboot_get_handoff_info((void **)&vboot_handoff, NULL) == 0)
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if (vboot_get_handoff_info((void **)&vboot_handoff, NULL) == 0)
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memcpy(&chromeos->vdat[0], &vboot_handoff->shared_data[0],
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memcpy(&chromeos_acpi->vdat[0], &vboot_handoff->shared_data[0],
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ARRAY_SIZE(chromeos->vdat));
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ARRAY_SIZE(chromeos_acpi->vdat));
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chromeos_ram_oops_init(chromeos);
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chromeos_ram_oops_init(chromeos_acpi);
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}
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}
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void chromeos_set_me_hash(u32 *hash, int len)
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void chromeos_set_me_hash(u32 *hash, int len)
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{
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{
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if ((len*sizeof(u32)) > sizeof(vboot_data->mehh))
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if ((len*sizeof(u32)) > sizeof(chromeos_acpi->mehh))
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return;
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return;
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/* Copy to NVS or save until it is ready */
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/* Copy to NVS or save until it is ready */
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if (vboot_data)
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if (chromeos_acpi)
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/* This does never happen! */
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/* This does never happen! */
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memcpy(vboot_data->mehh, hash, len*sizeof(u32));
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memcpy(chromeos_acpi->mehh, hash, len*sizeof(u32));
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else
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else
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memcpy(me_hash_saved, hash, len*sizeof(u32));
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memcpy(me_hash_saved, hash, len*sizeof(u32));
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}
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}
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void acpi_get_vdat_info(uint64_t *vdat_addr, uint32_t *vdat_size)
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void acpi_get_chromeos_acpi_info(uint64_t *chromeos_acpi_addr,
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uint32_t *chromeos_acpi_size)
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{
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{
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*vdat_addr = (intptr_t)vboot_data;
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*chromeos_acpi_addr = (intptr_t)chromeos_acpi;
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*vdat_size = sizeof(*vboot_data);
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*chromeos_acpi_size = sizeof(*chromeos_acpi);
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}
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chromeos_acpi_t *acpi_get_chromeos_acpi(void)
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{
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return chromeos_acpi;
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}
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}
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@ -53,7 +53,7 @@ typedef struct {
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u32 vbt7; // 18e active main firmware type
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u32 vbt7; // 18e active main firmware type
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u32 vbt8; // 192 recovery reason
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u32 vbt8; // 192 recovery reason
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u32 vbt9; // 196 fmap base address
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u32 vbt9; // 196 fmap base address
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u8 vdat[3072]; // 19a
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u8 vdat[3072]; // 19a VDAT space filled by verified boot
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u32 vbt10; // d9a smbios bios version
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u32 vbt10; // d9a smbios bios version
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u32 mehh[8]; // d9e management engine hash
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u32 mehh[8]; // d9e management engine hash
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u32 ramoops_base; // dbe ramoops base address
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u32 ramoops_base; // dbe ramoops base address
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u8 pad[314]; // dc6-eff
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u8 pad[314]; // dc6-eff
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} __packed chromeos_acpi_t;
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} __packed chromeos_acpi_t;
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extern chromeos_acpi_t *vboot_data;
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void chromeos_init_vboot(chromeos_acpi_t *init);
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void chromeos_init_vboot(chromeos_acpi_t *chromeos);
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void chromeos_set_me_hash(u32*, int);
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void chromeos_set_me_hash(u32*, int);
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void acpi_get_vdat_info(uint64_t *vdat_addr, uint32_t *vdat_size);
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void acpi_get_chromeos_acpi_info(uint64_t *chromeos_acpi_addr,
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uint32_t *chromeos_acpi_size);
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chromeos_acpi_t *acpi_get_chromeos_acpi(void);
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#endif
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#endif
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