update SOLO code (untested but compiling and pretty much complete!?!)
drop old configuration method. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1102 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
parent
ff0e8465e8
commit
75d42640d5
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@ -1,186 +1,179 @@
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#
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uses HAVE_MP_TABLE
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uses HAVE_PIRQ_TABLE
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uses USE_FALLBACK_IMAGE
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uses MAINBOARD
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uses ARCH
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uses FALLBACK_SIZE
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uses ROM_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_IMAGE_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_SECTION_OFFSET
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uses CONFIG_ROM_STREAM_START
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uses PAYLOAD_SIZE
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uses _ROMBASE
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uses XIP_ROM_SIZE
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uses XIP_ROM_BASE
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###
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### Build code to export a CMOS option table
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###
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default HAVE_OPTION_TABLE=1
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option HAVE_MP_TABLE=0
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####
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#### Build options
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####
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#
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###
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### Location of the DIMM EEPROMS on the SMBUS
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### This is fixed into a narrow range by the DIMM package standard.
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###
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option SMBUS_MEM_DEVICE_START=(0xa << 3)
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option SMBUS_MEM_DEVICE_END=(SMBUS_MEM_DEVICE_START +1)
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option SMBUS_MEM_DEVICE_INC=1
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default CONFIG_CONSOLE_VGA=0
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default CONFIG_CONSOLE_LOGBUF=0
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default CONFIG_CONSOLE_SROM=0
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default CONFIG_SMP=0
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default CONFIG_UDELAY_TSC=0
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#
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###
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### Customize our winbond superio chip for this motherboard
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###
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option CONFIG_CONSOLE_SERIAL8250=0
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#
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###
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### Build code for the fallback boot
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### Build options
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###
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##
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## Build code for the fallback boot
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##
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option HAVE_FALLBACK_BOOT=1
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#
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###
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### Build code to reset the motherboard from linuxBIOS
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###
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## option HAVE_HARD_RESET=1
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#
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###
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### Build code to export a programmable irq routing table
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###
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##
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## Build code to reset the motherboard from linuxBIOS
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##
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option HAVE_HARD_RESET=1
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##
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## Build code to export a programmable irq routing table
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##
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option HAVE_PIRQ_TABLE=1
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option IRQ_SLOT_COUNT=7
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#
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###
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### Build code to export an x86 MP table
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### Useful for specifying IRQ routing values
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###
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##option HAVE_MP_TABLE=1
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#
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###
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### Build code for SMP support
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### Only worry about 2 micro processors
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###
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##option CONFIG_SMP=1
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##
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## Build code to export an x86 MP table
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## Useful for specifying IRQ routing values
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##
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option HAVE_MP_TABLE=1
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##
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## Build code to export a CMOS option table
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##
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option HAVE_OPTION_TABLE=1
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##
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## AMD Solo is a 1cpu board
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##
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option CONFIG_SMP=0
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option CONFIG_MAX_CPUS=1
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#
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###
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### Build code to setup a generic IOAPIC
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###
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##
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## Build code to setup a generic IOAPIC
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##
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option CONFIG_IOAPIC=1
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#
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###
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### MEMORY_HOLE instructs earlymtrr.inc to
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### enable caching from 0-640KB and to disable
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### caching from 640KB-1MB using fixed MTRRs
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###
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### Enabling this option breaks SMP because secondary
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### CPU identification depends on only variable MTRRs
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### being enabled.
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###
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option MEMORY_HOLE=0
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#
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###
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### Clean up the motherboard id strings
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###
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option MAINBOARD_PART_NUMBER="Solo7"
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##
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## Clean up the motherboard id strings
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##
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option MAINBOARD_PART_NUMBER="SOLO7"
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option MAINBOARD_VENDOR="AMD"
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#
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###
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### Figure out which type of linuxBIOS image to build
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### If we aren't a fallback image we must be a normal image
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### This is useful for optional includes
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###
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default USE_FALLBACK_IMAGE=0
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#
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####
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#### LinuxBIOS layout values
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####
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#
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### ROM_SIZE is the size of boot ROM that this board will use.
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option ROM_SIZE=262144
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#
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### ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
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option ROM_IMAGE_SIZE=65535
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#
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###
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### Use a small 8K stack
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### LinuxBIOS layout values
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###
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## ROM_SIZE is the size of boot ROM that this board will use.
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option ROM_SIZE = 262144
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## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
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option ROM_IMAGE_SIZE = 65536
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##
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## Use a small 8K stack
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##
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option STACK_SIZE=0x2000
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#
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###
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### Use a small 8K heap
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###
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option HEAP_SIZE=0x2000
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#
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###
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### Only use the option table in a normal image
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###
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option USE_OPTION_TABLE=!USE_FALLBACK_IMAGE
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#
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###
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### Compute the location and size of where this firmware image
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### (linuxBIOS plus bootloader) will live in the boot rom chip.
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###
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default FALLBACK_SIZE=65536
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if USE_FALLBACK_IMAGE
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option ROM_SECTION_SIZE = FALLBACK_SIZE
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option ROM_SECTION_OFFSET= (ROM_SIZE - FALLBACK_SIZE)
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##
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## Use a small 16K heap
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##
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option HEAP_SIZE=0x4000
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##
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## Only use the option table in a normal image
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##
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option USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
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##
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## Compute the location and size of where this firmware image
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## (linuxBIOS plus bootloader) will live in the boot rom chip.
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##
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if USE_FALLBACK_IMAGE
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option ROM_SECTION_SIZE = FALLBACK_SIZE
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option ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
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else
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option ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
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option ROM_SECTION_OFFSET= 0
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option ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
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option ROM_SECTION_OFFSET = 0
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end
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#
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###
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### Compute the start location and size size of
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### The linuxBIOS bootloader.
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###
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option PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
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##
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## Compute the start location and size size of
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## The linuxBIOS bootloader.
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##
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option PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
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option CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
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option CONFIG_ROM_STREAM = 1
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#
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###
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### Compute where this copy of linuxBIOS will start in the boot rom
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###
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option _ROMBASE = (CONFIG_ROM_STREAM_START + PAYLOAD_SIZE)
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#
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###
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### Compute a range of ROM that can cached to speed up linuxBIOS,
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### execution speed.
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###
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##expr XIP_ROM_SIZE = 65536
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##expr XIP_ROM_BASE = _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE
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##option XIP_ROM_SIZE=65536
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##option XIP_ROM_BASE=0xffff0000
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#
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## XIP_ROM_SIZE && XIP_ROM_BASE values that work.
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##option XIP_ROM_SIZE=0x8000
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##option XIP_ROM_BASE=0xffff8000
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#
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###
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### Set all of the defaults for an x86 architecture
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###
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#
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#
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###
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### Build the objects we have code for in this directory.
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###
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##object mainboard.o
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##
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## Compute where this copy of linuxBIOS will start in the boot rom
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##
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option _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
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##
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## Compute a range of ROM that can cached to speed up linuxBIOS,
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## execution speed.
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##
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## XIP_ROM_SIZE must be a power of 2.
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## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
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##
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option XIP_ROM_SIZE=65536
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option XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
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##
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## Set all of the defaults for an x86 architecture
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##
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arch i386 end
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#cpu k8 end
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##
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## Build the objects we have code for in this directory.
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##
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#object mainboard.o
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driver mainboard.o
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object static_devices.o
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#object static_devices.o
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if HAVE_MP_TABLE object mptable.o end
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if HAVE_PIRQ_TABLE object irq_tables.o end
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#
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arch i386 end
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cpu k8 end
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#
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option DEBUG=1
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default USE_FALLBACK_IMAGE=1
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option A=(1+2)
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option B=0xa
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#
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###
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### Build our 16 bit and 32 bit linuxBIOS entry code
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###
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object reset.o
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##
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## Romcc output
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##
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makerule ./failover.E
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depends "$(MAINBOARD)/failover.c"
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action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
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end
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makerule ./failover.inc
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depends "./failover.E ./romcc"
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action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
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end
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makerule ./auto.E
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depends "$(MAINBOARD)/auto.c"
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action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
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end
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makerule ./auto.inc
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depends "./auto.E ./romcc"
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action "./romcc -mcpu=k8 -O ./auto.E > auto.inc"
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end
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##
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## Build our 16 bit and 32 bit linuxBIOS entry code
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##
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mainboardinit cpu/i386/entry16.inc
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mainboardinit cpu/i386/entry32.inc
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ldscript /cpu/i386/entry16.lds
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ldscript /cpu/i386/entry32.lds
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#
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###
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### Build our reset vector (This is where linuxBIOS is entered)
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###
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##
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## Build our reset vector (This is where linuxBIOS is entered)
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##
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/i386/reset16.inc
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ldscript /cpu/i386/reset16.lds
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@ -188,74 +181,92 @@ else
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mainboardinit cpu/i386/reset32.inc
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ldscript /cpu/i386/reset32.lds
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end
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#
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#### Should this be in the northbridge code?
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#mainboardinit archi386/lib/cpu_reset.inc
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#
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###
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### Include an id string (For safe flashing)
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###
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### Should this be in the northbridge code?
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mainboardinit arch/i386/lib/cpu_reset.inc
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##
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## Include an id string (For safe flashing)
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##
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mainboardinit arch/i386/lib/id.inc
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ldscript /arch/i386/lib/id.lds
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#
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####
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#### This is the early phase of linuxBIOS startup
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#### Things are delicate and we test to see if we should
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#### failover to another image.
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####
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option MAX_REBOOT_CNT=2
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if USE_FALLBACK_IMAGE
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ldscript /arch/i386/lib/failover.lds
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end
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#
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###
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### Setup our mtrrs
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###
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##
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## Setup our mtrrs
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##
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mainboardinit cpu/k8/earlymtrr.inc
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#
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#
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####
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#### O.k. We aren't just an intermediary anymore!
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####
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#
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###
|
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### When debugging disable the watchdog timer
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### This is the early phase of linuxBIOS startup
|
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### Things are delicate and we test to see if we should
|
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### failover to another image.
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###
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##option MAXIMUM_CONSOLE_LOGLEVEL=7
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#default MAXIMUM_CONSOLE_LOGLEVEL=7
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#
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if USE_FALLBACK_IMAGE
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ldscript /arch/i386/lib/failover.lds
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mainboardinit ./failover.inc
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end
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###
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### Setup the serial port
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### O.k. We aren't just an intermediary anymore!
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###
|
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#mainboardinit superiowinbond/w83627hf/setup_serial.inc
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##
|
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## Setup RAM
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##
|
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mainboardinit cpu/k8/enable_mmx_sse.inc
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mainboardinit ./auto.inc
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mainboardinit cpu/k8/disable_mmx_sse.inc
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##
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## Include the secondary Configuration files
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##
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dir /pc80
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config chip.h
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northbridge amd/amdk8 "mc0"
|
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pci 0:18.0
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pci 0:18.0
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pci 0:18.0
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pci 0:18.1
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pci 0:18.2
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pci 0:18.3
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southbridge amd/amd8111 "amd8111"
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pci 0:0.0
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pci 0:1.0
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pci 0:1.1
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pci 0:1.2
|
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pci 0:1.3
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pci 0:1.5
|
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pci 0:1.6
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superio NSC/pc87360
|
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pnp 1:2e.0
|
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pnp 1:2e.1
|
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pnp 1:2e.2
|
||||
pnp 1:2e.3
|
||||
pnp 1:2e.4
|
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pnp 1:2e.5
|
||||
pnp 1:2e.6
|
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pnp 1:2e.7
|
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pnp 1:2e.8
|
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pnp 1:2e.9
|
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pnp 1:2e.a
|
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register "com1" = "{1, 0, 0x3f8, 4}"
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register "lpt" = "{1}"
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end
|
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end
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southbridge amd/amd8151 "amd8151"
|
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pci 0:0.0
|
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pci 0:1.0
|
||||
end
|
||||
end
|
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|
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cpu k8 "cpu0"
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register "up" = "{ .chip = &amd8111, .ht_width=16, .ht_speed=600 }"
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end
|
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|
||||
##
|
||||
## Include the old serial code for those few places that still need it.
|
||||
##
|
||||
mainboardinit pc80/serial.inc
|
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mainboardinit arch/i386/lib/console.inc
|
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if USE_FALLBACK_IMAGE mainboardinit archi386/lib/noop_failover.inc end
|
||||
#
|
||||
###
|
||||
### Romcc output
|
||||
###
|
||||
#makerule ./failover.E dep "$(MAINBOARD)/failover.c" act "$(CPP) -I$(TOP)/src $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failever.E"
|
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#makerule ./failover.inc dep "./romcc ./failover.E" act "./romcc -O ./failover.E > failover.inc"
|
||||
#mainboardinit .failover.inc
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makerule ./auto.E dep "$(MAINBOARD)/auto.c" act "$(CPP) -I$(TOP)/src -$(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
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makerule ./auto.inc dep "./romcc ./auto.E" act "./romcc -O ./auto.E > auto.inc"
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mainboardinit ./auto.inc
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#
|
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###
|
||||
### Include the secondary Configuration files
|
||||
###
|
||||
northbridge amd/amdk8
|
||||
end
|
||||
southbridge amd/amd8111
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||||
end
|
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#mainboardinit archi386/smp/secondary.inc
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superio NSC/pc87360
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register "com1={1} com2={0} floppy=1 lpt=1 keyboard=1"
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end
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dir /pc80
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##dir /src/superio/winbond/w83627hf
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cpu p5 end
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||||
cpu p6 end
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||||
cpu k7 end
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cpu k8 end
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||||
|
||||
|
|
|
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|
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@ -1,6 +1,4 @@
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#define ASSEMBLY 1
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#define MAXIMUM_CONSOLE_LOGLEVEL 9
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#define DEFAULT_CONSOLE_LOGLEVEL 9
|
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|
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#include <stdint.h>
|
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#include <device/pci_def.h>
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|
|
@ -20,12 +18,21 @@
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#include "northbridge/amd/amdk8/reset_test.c"
|
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#include "debug.c"
|
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|
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#define SIO_BASE 0x2e
|
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|
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static void memreset_setup(void)
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{
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/* Set the memreset low */
|
||||
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
|
||||
/* Ensure the BIOS has control of the memory lines */
|
||||
}
|
||||
|
||||
static void memreset(int controllers, const struct mem_controller *ctrl)
|
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{
|
||||
udelay(800);
|
||||
/* Set memreset_high */
|
||||
outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
|
||||
udelay(90);
|
||||
}
|
||||
|
||||
static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
|
||||
|
|
@ -87,6 +94,26 @@ static void stop_this_cpu(void)
|
|||
}
|
||||
}
|
||||
|
||||
#define PC87360_FDC 0x00
|
||||
#define PC87360_PP 0x01
|
||||
#define PC87360_SP2 0x02
|
||||
#define PC87360_SP1 0x03
|
||||
#define PC87360_SWC 0x04
|
||||
#define PC87360_KBCM 0x05
|
||||
#define PC87360_KBCK 0x06
|
||||
#define PC87360_GPIO 0x07
|
||||
#define PC87360_ACB 0x08
|
||||
#define PC87360_FSCM 0x09
|
||||
#define PC87360_WDT 0x0A
|
||||
|
||||
/* FIXME: Do we really need this on Solo boards? */
|
||||
static void pc87360_enable_serial(void)
|
||||
{
|
||||
pnp_set_logical_device(SIO_BASE, PC87360_SP1);
|
||||
pnp_set_enable(SIO_BASE, 1);
|
||||
pnp_set_iobase0(SIO_BASE, 0x3f8);
|
||||
}
|
||||
|
||||
static void main(void)
|
||||
{
|
||||
/*
|
||||
|
|
@ -111,11 +138,14 @@ static void main(void)
|
|||
enable_lapic();
|
||||
init_timer();
|
||||
|
||||
/* Solo boards only have 1 CPU, this check is not needed!? */
|
||||
if (!boot_cpu()) {
|
||||
notify_bsp_ap_is_stopped();
|
||||
stop_this_cpu();
|
||||
}
|
||||
|
||||
pc87360_enable_serial();
|
||||
|
||||
uart_init();
|
||||
console_init();
|
||||
setup_default_resource_map();
|
||||
|
|
|
|||
|
|
@ -0,0 +1,5 @@
|
|||
struct chip_control mainboard_amd_solo_control;
|
||||
|
||||
struct mainboard_amd_solo_config {
|
||||
int nothing;
|
||||
};
|
||||
|
|
@ -1,11 +1,42 @@
|
|||
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
|
||||
#include <arch/io.h>
|
||||
#include <device/chip.h>
|
||||
#include "../../../northbridge/amd/amdk8/northbridge.h"
|
||||
#include "chip.h"
|
||||
|
||||
|
||||
unsigned long initial_apicid[CONFIG_MAX_CPUS] =
|
||||
{
|
||||
0
|
||||
0,
|
||||
};
|
||||
|
||||
static struct device_operations mainboard_operations = {
|
||||
.read_resources = root_dev_read_resources,
|
||||
.set_resources = root_dev_set_resources,
|
||||
.enable_resources = enable_childrens_resources,
|
||||
.init = 0,
|
||||
.scan_bus = amdk8_scan_root_bus,
|
||||
.enable = 0,
|
||||
};
|
||||
|
||||
static void enumerate(struct chip *chip)
|
||||
{
|
||||
struct chip *child;
|
||||
dev_root.ops = &mainboard_operations;
|
||||
chip->dev = &dev_root;
|
||||
chip->bus = 0;
|
||||
for(child = chip->children; child; child = child->next) {
|
||||
child->bus = &dev_root.link[0];
|
||||
}
|
||||
}
|
||||
struct chip_control mainboard_amd_solo_control = {
|
||||
.enumerate = enumerate,
|
||||
.name = "AMD Solo7 mainboard ",
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue