util/msrtool: Fix typos
Change-Id: I36ed2c33f9bed3e640871283c2cb163d6800d1d5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
parent
403458e7ec
commit
75db596654
|
@ -278,7 +278,7 @@ const struct msrdef intel_atom_msrs[] = {
|
||||||
}},
|
}},
|
||||||
{ 1, 1, "VMX inside of SMX operation", "R/WL", PRESENT_BIN, {
|
{ 1, 1, "VMX inside of SMX operation", "R/WL", PRESENT_BIN, {
|
||||||
/* This bit enables a system executive to use
|
/* This bit enables a system executive to use
|
||||||
* VMX in conjuction with SMX to support Intel
|
* VMX in conjunction with SMX to support Intel
|
||||||
* Trusted Execution Technology.
|
* Trusted Execution Technology.
|
||||||
*/
|
*/
|
||||||
{ MSR1(0), "VMX inside of SMX operation disabled" },
|
{ MSR1(0), "VMX inside of SMX operation disabled" },
|
||||||
|
@ -797,9 +797,9 @@ const struct msrdef intel_atom_msrs[] = {
|
||||||
/* if CPUID.0AH EAX[7:0] > 2 */
|
/* if CPUID.0AH EAX[7:0] > 2 */
|
||||||
{ 10, 1, "AnyThread 2", "R/W", PRESENT_BIN, {
|
{ 10, 1, "AnyThread 2", "R/W", PRESENT_BIN, {
|
||||||
{ MSR1(0), "Counter only increments the associated event \
|
{ MSR1(0), "Counter only increments the associated event \
|
||||||
conditions occuring in the logical processor which programmed the MSR" },
|
conditions occurring in the logical processor which programmed the MSR" },
|
||||||
{ MSR1(1), "Counting the associated event conditions \
|
{ MSR1(1), "Counting the associated event conditions \
|
||||||
occuring across all logical processors sharing a processor core" },
|
occurring across all logical processors sharing a processor core" },
|
||||||
{ BITVAL_EOT }
|
{ BITVAL_EOT }
|
||||||
}},
|
}},
|
||||||
{ 9, 1, "EN2_Usr", "R/W", PRESENT_BIN, {
|
{ 9, 1, "EN2_Usr", "R/W", PRESENT_BIN, {
|
||||||
|
@ -820,9 +820,9 @@ const struct msrdef intel_atom_msrs[] = {
|
||||||
/* if CPUID.0AH: EAX[7:0] > 2 */
|
/* if CPUID.0AH: EAX[7:0] > 2 */
|
||||||
{ 6, 1, "AnyThread 1", "R/W", PRESENT_BIN, {
|
{ 6, 1, "AnyThread 1", "R/W", PRESENT_BIN, {
|
||||||
{ MSR1(0), "Counter only increments the associated event \
|
{ MSR1(0), "Counter only increments the associated event \
|
||||||
conditions occuring in the logical processor which programmed the MSR" },
|
conditions occurring in the logical processor which programmed the MSR" },
|
||||||
{ MSR1(1), "Counting the associated event conditions \
|
{ MSR1(1), "Counting the associated event conditions \
|
||||||
occuring across all logical processors sharing a processor core" },
|
occurring across all logical processors sharing a processor core" },
|
||||||
{ BITVAL_EOT }
|
{ BITVAL_EOT }
|
||||||
}},
|
}},
|
||||||
{ 5, 1, "EN1_Usr", "R/W", PRESENT_BIN, {
|
{ 5, 1, "EN1_Usr", "R/W", PRESENT_BIN, {
|
||||||
|
@ -843,9 +843,9 @@ const struct msrdef intel_atom_msrs[] = {
|
||||||
/* if CPUID.0AH: EAX[7:0] > 2 */
|
/* if CPUID.0AH: EAX[7:0] > 2 */
|
||||||
{ 2, 1, "AnyThread 0", "R/W", PRESENT_BIN, {
|
{ 2, 1, "AnyThread 0", "R/W", PRESENT_BIN, {
|
||||||
{ MSR1(0), "Counter only increments the associated event \
|
{ MSR1(0), "Counter only increments the associated event \
|
||||||
conditions occuring in the logical processor which programmed the MSR" },
|
conditions occurring in the logical processor which programmed the MSR" },
|
||||||
{ MSR1(1), "Counting the associated event conditions \
|
{ MSR1(1), "Counting the associated event conditions \
|
||||||
occuring across all logical processors sharing a processor core" },
|
occurring across all logical processors sharing a processor core" },
|
||||||
{ BITVAL_EOT }
|
{ BITVAL_EOT }
|
||||||
}},
|
}},
|
||||||
{ 1, 1, "EN0_Usr", "R/W", PRESENT_BIN, {
|
{ 1, 1, "EN0_Usr", "R/W", PRESENT_BIN, {
|
||||||
|
|
|
@ -232,7 +232,7 @@ const struct msrdef intel_core2_later_msrs[] = {
|
||||||
}},
|
}},
|
||||||
{ 1, 1, "VMX inside of SMX operation", "R/WL", PRESENT_BIN, {
|
{ 1, 1, "VMX inside of SMX operation", "R/WL", PRESENT_BIN, {
|
||||||
/* This bit enables a system executive to use
|
/* This bit enables a system executive to use
|
||||||
* VMX in conjuction with SMX to support Intel
|
* VMX in conjunction with SMX to support Intel
|
||||||
* Trusted Execution Technology.
|
* Trusted Execution Technology.
|
||||||
*/
|
*/
|
||||||
{ MSR1(0), "VMX inside of SMX operation disabled" },
|
{ MSR1(0), "VMX inside of SMX operation disabled" },
|
||||||
|
@ -821,9 +821,9 @@ const struct msrdef intel_core2_later_msrs[] = {
|
||||||
/* if CPUID.0AH EAX[7:0] > 2 */
|
/* if CPUID.0AH EAX[7:0] > 2 */
|
||||||
{ 10, 1, "AnyThread 2", "R/W", PRESENT_BIN, {
|
{ 10, 1, "AnyThread 2", "R/W", PRESENT_BIN, {
|
||||||
{ MSR1(0), "Counter only increments the associated event \
|
{ MSR1(0), "Counter only increments the associated event \
|
||||||
conditions occuring in the logical processor which programmed the MSR" },
|
conditions occurring in the logical processor which programmed the MSR" },
|
||||||
{ MSR1(1), "Counting the associated event conditions \
|
{ MSR1(1), "Counting the associated event conditions \
|
||||||
occuring across all logical processors sharing a processor core" },
|
occurring across all logical processors sharing a processor core" },
|
||||||
{ BITVAL_EOT }
|
{ BITVAL_EOT }
|
||||||
}},
|
}},
|
||||||
{ 9, 1, "EN2_Usr", "R/W", PRESENT_BIN, {
|
{ 9, 1, "EN2_Usr", "R/W", PRESENT_BIN, {
|
||||||
|
@ -844,9 +844,9 @@ const struct msrdef intel_core2_later_msrs[] = {
|
||||||
/* if CPUID.0AH: EAX[7:0] > 2 */
|
/* if CPUID.0AH: EAX[7:0] > 2 */
|
||||||
{ 6, 1, "AnyThread 1", "R/W", PRESENT_BIN, {
|
{ 6, 1, "AnyThread 1", "R/W", PRESENT_BIN, {
|
||||||
{ MSR1(0), "Counter only increments the associated event \
|
{ MSR1(0), "Counter only increments the associated event \
|
||||||
conditions occuring in the logical processor which programmed the MSR" },
|
conditions occurring in the logical processor which programmed the MSR" },
|
||||||
{ MSR1(1), "Counting the associated event conditions \
|
{ MSR1(1), "Counting the associated event conditions \
|
||||||
occuring across all logical processors sharing a processor core" },
|
occurring across all logical processors sharing a processor core" },
|
||||||
{ BITVAL_EOT }
|
{ BITVAL_EOT }
|
||||||
}},
|
}},
|
||||||
{ 5, 1, "EN1_Usr", "R/W", PRESENT_BIN, {
|
{ 5, 1, "EN1_Usr", "R/W", PRESENT_BIN, {
|
||||||
|
@ -867,9 +867,9 @@ const struct msrdef intel_core2_later_msrs[] = {
|
||||||
/* if CPUID.0AH: EAX[7:0] > 2 */
|
/* if CPUID.0AH: EAX[7:0] > 2 */
|
||||||
{ 2, 1, "AnyThread 0", "R/W", PRESENT_BIN, {
|
{ 2, 1, "AnyThread 0", "R/W", PRESENT_BIN, {
|
||||||
{ MSR1(0), "Counter only increments the associated event \
|
{ MSR1(0), "Counter only increments the associated event \
|
||||||
conditions occuring in the logical processor which programmed the MSR" },
|
conditions occurring in the logical processor which programmed the MSR" },
|
||||||
{ MSR1(1), "Counting the associated event conditions \
|
{ MSR1(1), "Counting the associated event conditions \
|
||||||
occuring across all logical processors sharing a processor core" },
|
occurring across all logical processors sharing a processor core" },
|
||||||
{ BITVAL_EOT }
|
{ BITVAL_EOT }
|
||||||
}},
|
}},
|
||||||
{ 1, 1, "EN0_Usr", "R/W", PRESENT_BIN, {
|
{ 1, 1, "EN0_Usr", "R/W", PRESENT_BIN, {
|
||||||
|
|
|
@ -307,7 +307,7 @@ const struct msrdef intel_nehalem_msrs[] = {
|
||||||
}},
|
}},
|
||||||
{ 1, 1, "VMX inside of SMX operation", "R/WL", PRESENT_BIN, {
|
{ 1, 1, "VMX inside of SMX operation", "R/WL", PRESENT_BIN, {
|
||||||
/* This bit enables a system executive to use
|
/* This bit enables a system executive to use
|
||||||
* VMX in conjuction with SMX to support Intel
|
* VMX in conjunction with SMX to support Intel
|
||||||
* Trusted Execution Technology.
|
* Trusted Execution Technology.
|
||||||
*/
|
*/
|
||||||
{ MSR1(0), "VMX inside of SMX operation disabled" },
|
{ MSR1(0), "VMX inside of SMX operation disabled" },
|
||||||
|
@ -1109,7 +1109,7 @@ const struct msrdef intel_nehalem_msrs[] = {
|
||||||
/* Whole package bit */
|
/* Whole package bit */
|
||||||
{ 1, 1, "C1E Enable", "R/W", PRESENT_BIN, {
|
{ 1, 1, "C1E Enable", "R/W", PRESENT_BIN, {
|
||||||
{ MSR1(0), "Nothing" },
|
{ MSR1(0), "Nothing" },
|
||||||
{ MSR1(1), "CPU switch to the Minimum Enhaced Intel \
|
{ MSR1(1), "CPU switch to the Minimum Enhanced Intel \
|
||||||
SpeedStep Technology operating point when all \
|
SpeedStep Technology operating point when all \
|
||||||
execution cores enter MWAIT (C1)" },
|
execution cores enter MWAIT (C1)" },
|
||||||
{ BITVAL_EOT }
|
{ BITVAL_EOT }
|
||||||
|
@ -1373,9 +1373,9 @@ const struct msrdef intel_nehalem_msrs[] = {
|
||||||
/* if CPUID.0AH EAX[7:0] > 2 */
|
/* if CPUID.0AH EAX[7:0] > 2 */
|
||||||
{ 10, 1, "AnyThread 2", "R/W", PRESENT_BIN, {
|
{ 10, 1, "AnyThread 2", "R/W", PRESENT_BIN, {
|
||||||
{ MSR1(0), "Counter only increments the associated event \
|
{ MSR1(0), "Counter only increments the associated event \
|
||||||
conditions occuring in the logical processor which programmed the MSR" },
|
conditions occurring in the logical processor which programmed the MSR" },
|
||||||
{ MSR1(1), "Counting the associated event conditions \
|
{ MSR1(1), "Counting the associated event conditions \
|
||||||
occuring across all logical processors sharing a processor core" },
|
occurring across all logical processors sharing a processor core" },
|
||||||
{ BITVAL_EOT }
|
{ BITVAL_EOT }
|
||||||
}},
|
}},
|
||||||
{ 9, 1, "EN2_Usr", "R/W", PRESENT_BIN, {
|
{ 9, 1, "EN2_Usr", "R/W", PRESENT_BIN, {
|
||||||
|
@ -1396,9 +1396,9 @@ const struct msrdef intel_nehalem_msrs[] = {
|
||||||
/* if CPUID.0AH: EAX[7:0] > 2 */
|
/* if CPUID.0AH: EAX[7:0] > 2 */
|
||||||
{ 6, 1, "AnyThread 1", "R/W", PRESENT_BIN, {
|
{ 6, 1, "AnyThread 1", "R/W", PRESENT_BIN, {
|
||||||
{ MSR1(0), "Counter only increments the associated event \
|
{ MSR1(0), "Counter only increments the associated event \
|
||||||
conditions occuring in the logical processor which programmed the MSR" },
|
conditions occurring in the logical processor which programmed the MSR" },
|
||||||
{ MSR1(1), "Counting the associated event conditions \
|
{ MSR1(1), "Counting the associated event conditions \
|
||||||
occuring across all logical processors sharing a processor core" },
|
occurring across all logical processors sharing a processor core" },
|
||||||
{ BITVAL_EOT }
|
{ BITVAL_EOT }
|
||||||
}},
|
}},
|
||||||
{ 5, 1, "EN1_Usr", "R/W", PRESENT_BIN, {
|
{ 5, 1, "EN1_Usr", "R/W", PRESENT_BIN, {
|
||||||
|
@ -1419,9 +1419,9 @@ const struct msrdef intel_nehalem_msrs[] = {
|
||||||
/* if CPUID.0AH: EAX[7:0] > 2 */
|
/* if CPUID.0AH: EAX[7:0] > 2 */
|
||||||
{ 2, 1, "AnyThread 0", "R/W", PRESENT_BIN, {
|
{ 2, 1, "AnyThread 0", "R/W", PRESENT_BIN, {
|
||||||
{ MSR1(0), "Counter only increments the associated event \
|
{ MSR1(0), "Counter only increments the associated event \
|
||||||
conditions occuring in the logical processor which programmed the MSR" },
|
conditions occurring in the logical processor which programmed the MSR" },
|
||||||
{ MSR1(1), "Counting the associated event conditions \
|
{ MSR1(1), "Counting the associated event conditions \
|
||||||
occuring across all logical processors sharing a processor core" },
|
occurring across all logical processors sharing a processor core" },
|
||||||
{ BITVAL_EOT }
|
{ BITVAL_EOT }
|
||||||
}},
|
}},
|
||||||
{ 1, 1, "EN0_Usr", "R/W", PRESENT_BIN, {
|
{ 1, 1, "EN0_Usr", "R/W", PRESENT_BIN, {
|
||||||
|
|
Loading…
Reference in New Issue