util/msrtool: Fix typos
Change-Id: I36ed2c33f9bed3e640871283c2cb163d6800d1d5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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@ -278,7 +278,7 @@ const struct msrdef intel_atom_msrs[] = {
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}},
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{ 1, 1, "VMX inside of SMX operation", "R/WL", PRESENT_BIN, {
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/* This bit enables a system executive to use
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* VMX in conjuction with SMX to support Intel
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* VMX in conjunction with SMX to support Intel
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* Trusted Execution Technology.
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*/
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{ MSR1(0), "VMX inside of SMX operation disabled" },
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@ -797,9 +797,9 @@ const struct msrdef intel_atom_msrs[] = {
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/* if CPUID.0AH EAX[7:0] > 2 */
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{ 10, 1, "AnyThread 2", "R/W", PRESENT_BIN, {
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{ MSR1(0), "Counter only increments the associated event \
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conditions occuring in the logical processor which programmed the MSR" },
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conditions occurring in the logical processor which programmed the MSR" },
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{ MSR1(1), "Counting the associated event conditions \
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occuring across all logical processors sharing a processor core" },
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occurring across all logical processors sharing a processor core" },
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{ BITVAL_EOT }
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}},
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{ 9, 1, "EN2_Usr", "R/W", PRESENT_BIN, {
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@ -820,9 +820,9 @@ const struct msrdef intel_atom_msrs[] = {
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/* if CPUID.0AH: EAX[7:0] > 2 */
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{ 6, 1, "AnyThread 1", "R/W", PRESENT_BIN, {
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{ MSR1(0), "Counter only increments the associated event \
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conditions occuring in the logical processor which programmed the MSR" },
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conditions occurring in the logical processor which programmed the MSR" },
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{ MSR1(1), "Counting the associated event conditions \
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occuring across all logical processors sharing a processor core" },
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occurring across all logical processors sharing a processor core" },
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{ BITVAL_EOT }
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}},
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{ 5, 1, "EN1_Usr", "R/W", PRESENT_BIN, {
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@ -843,9 +843,9 @@ const struct msrdef intel_atom_msrs[] = {
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/* if CPUID.0AH: EAX[7:0] > 2 */
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{ 2, 1, "AnyThread 0", "R/W", PRESENT_BIN, {
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{ MSR1(0), "Counter only increments the associated event \
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conditions occuring in the logical processor which programmed the MSR" },
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conditions occurring in the logical processor which programmed the MSR" },
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{ MSR1(1), "Counting the associated event conditions \
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occuring across all logical processors sharing a processor core" },
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occurring across all logical processors sharing a processor core" },
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{ BITVAL_EOT }
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}},
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{ 1, 1, "EN0_Usr", "R/W", PRESENT_BIN, {
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@ -232,7 +232,7 @@ const struct msrdef intel_core2_later_msrs[] = {
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}},
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{ 1, 1, "VMX inside of SMX operation", "R/WL", PRESENT_BIN, {
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/* This bit enables a system executive to use
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* VMX in conjuction with SMX to support Intel
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* VMX in conjunction with SMX to support Intel
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* Trusted Execution Technology.
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*/
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{ MSR1(0), "VMX inside of SMX operation disabled" },
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@ -821,9 +821,9 @@ const struct msrdef intel_core2_later_msrs[] = {
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/* if CPUID.0AH EAX[7:0] > 2 */
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{ 10, 1, "AnyThread 2", "R/W", PRESENT_BIN, {
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{ MSR1(0), "Counter only increments the associated event \
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conditions occuring in the logical processor which programmed the MSR" },
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conditions occurring in the logical processor which programmed the MSR" },
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{ MSR1(1), "Counting the associated event conditions \
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occuring across all logical processors sharing a processor core" },
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occurring across all logical processors sharing a processor core" },
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{ BITVAL_EOT }
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}},
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{ 9, 1, "EN2_Usr", "R/W", PRESENT_BIN, {
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@ -844,9 +844,9 @@ const struct msrdef intel_core2_later_msrs[] = {
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/* if CPUID.0AH: EAX[7:0] > 2 */
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{ 6, 1, "AnyThread 1", "R/W", PRESENT_BIN, {
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{ MSR1(0), "Counter only increments the associated event \
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conditions occuring in the logical processor which programmed the MSR" },
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conditions occurring in the logical processor which programmed the MSR" },
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{ MSR1(1), "Counting the associated event conditions \
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occuring across all logical processors sharing a processor core" },
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occurring across all logical processors sharing a processor core" },
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{ BITVAL_EOT }
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}},
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{ 5, 1, "EN1_Usr", "R/W", PRESENT_BIN, {
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@ -867,9 +867,9 @@ const struct msrdef intel_core2_later_msrs[] = {
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/* if CPUID.0AH: EAX[7:0] > 2 */
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{ 2, 1, "AnyThread 0", "R/W", PRESENT_BIN, {
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{ MSR1(0), "Counter only increments the associated event \
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conditions occuring in the logical processor which programmed the MSR" },
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conditions occurring in the logical processor which programmed the MSR" },
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{ MSR1(1), "Counting the associated event conditions \
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occuring across all logical processors sharing a processor core" },
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occurring across all logical processors sharing a processor core" },
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{ BITVAL_EOT }
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}},
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{ 1, 1, "EN0_Usr", "R/W", PRESENT_BIN, {
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@ -307,7 +307,7 @@ const struct msrdef intel_nehalem_msrs[] = {
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}},
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{ 1, 1, "VMX inside of SMX operation", "R/WL", PRESENT_BIN, {
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/* This bit enables a system executive to use
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* VMX in conjuction with SMX to support Intel
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* VMX in conjunction with SMX to support Intel
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* Trusted Execution Technology.
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*/
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{ MSR1(0), "VMX inside of SMX operation disabled" },
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@ -1109,7 +1109,7 @@ const struct msrdef intel_nehalem_msrs[] = {
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/* Whole package bit */
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{ 1, 1, "C1E Enable", "R/W", PRESENT_BIN, {
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{ MSR1(0), "Nothing" },
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{ MSR1(1), "CPU switch to the Minimum Enhaced Intel \
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{ MSR1(1), "CPU switch to the Minimum Enhanced Intel \
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SpeedStep Technology operating point when all \
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execution cores enter MWAIT (C1)" },
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{ BITVAL_EOT }
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@ -1373,9 +1373,9 @@ const struct msrdef intel_nehalem_msrs[] = {
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/* if CPUID.0AH EAX[7:0] > 2 */
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{ 10, 1, "AnyThread 2", "R/W", PRESENT_BIN, {
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{ MSR1(0), "Counter only increments the associated event \
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conditions occuring in the logical processor which programmed the MSR" },
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conditions occurring in the logical processor which programmed the MSR" },
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{ MSR1(1), "Counting the associated event conditions \
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occuring across all logical processors sharing a processor core" },
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occurring across all logical processors sharing a processor core" },
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{ BITVAL_EOT }
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}},
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{ 9, 1, "EN2_Usr", "R/W", PRESENT_BIN, {
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@ -1396,9 +1396,9 @@ const struct msrdef intel_nehalem_msrs[] = {
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/* if CPUID.0AH: EAX[7:0] > 2 */
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{ 6, 1, "AnyThread 1", "R/W", PRESENT_BIN, {
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{ MSR1(0), "Counter only increments the associated event \
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conditions occuring in the logical processor which programmed the MSR" },
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conditions occurring in the logical processor which programmed the MSR" },
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{ MSR1(1), "Counting the associated event conditions \
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occuring across all logical processors sharing a processor core" },
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occurring across all logical processors sharing a processor core" },
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{ BITVAL_EOT }
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}},
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{ 5, 1, "EN1_Usr", "R/W", PRESENT_BIN, {
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@ -1419,9 +1419,9 @@ const struct msrdef intel_nehalem_msrs[] = {
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/* if CPUID.0AH: EAX[7:0] > 2 */
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{ 2, 1, "AnyThread 0", "R/W", PRESENT_BIN, {
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{ MSR1(0), "Counter only increments the associated event \
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conditions occuring in the logical processor which programmed the MSR" },
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conditions occurring in the logical processor which programmed the MSR" },
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{ MSR1(1), "Counting the associated event conditions \
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occuring across all logical processors sharing a processor core" },
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occurring across all logical processors sharing a processor core" },
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{ BITVAL_EOT }
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}},
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{ 1, 1, "EN0_Usr", "R/W", PRESENT_BIN, {
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