diff --git a/src/mainboard/amd/inagua/devicetree.cb b/src/mainboard/amd/inagua/devicetree.cb
index 82658cffbc..32d9a2672c 100644
--- a/src/mainboard/amd/inagua/devicetree.cb
+++ b/src/mainboard/amd/inagua/devicetree.cb
@@ -71,6 +71,8 @@ chip northbridge/amd/agesa/family14/root_complex
 					device pci 15.1 on end # PCIe PortB
 					device pci 15.2 on end # PCIe PortC
 					device pci 15.3 on end # PCIe PortD
+					device pci 16.0 off end # OHCI USB3
+					device pci 16.2 off end # EHCI USB3
 					register "gpp_configuration" = "4" #1:1:1:1
 		  			register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
 				end	#southbridge/amd/cimx/sb800
diff --git a/src/mainboard/asrock/e350m1/devicetree.cb b/src/mainboard/asrock/e350m1/devicetree.cb
index bff8151fff..ca5cf2bce7 100644
--- a/src/mainboard/asrock/e350m1/devicetree.cb
+++ b/src/mainboard/asrock/e350m1/devicetree.cb
@@ -103,6 +103,8 @@ chip northbridge/amd/agesa/family14/root_complex
 					device pci 15.1 on  end # PCIe PortB: NIC
 					device pci 15.2 on  end # PCIe PortC: USB3
 					device pci 15.3 off end # PCIe PortD
+					device pci 16.0 off end # OHCI USB3
+					device pci 16.2 off end # EHCI USB3
 
 					# gpp_configuration options
 					#0000: PortA lanes[3:0]
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index b581212aed..c36ee03237 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -419,7 +419,9 @@ static void sb800_enable(device_t dev)
 	case (0x16 << 3) | 2: /* 0:16:2 EHCI-USB3 */
 		sb_config->USBMODE.UsbMode.Ehci3 = dev->enabled;
 
-		/* the last sb800 device */
+		/* call the CIMX entry at the last sb800 device,
+		 * so make sure the mainboard devicetree is complete
+		 */
 		sb_Before_Pci_Init();
 		break;