diff --git a/src/mainboard/google/volteer/Makefile.inc b/src/mainboard/google/volteer/Makefile.inc
index 6b5c065e1e..1b6b880806 100644
--- a/src/mainboard/google/volteer/Makefile.inc
+++ b/src/mainboard/google/volteer/Makefile.inc
@@ -9,6 +9,7 @@
 bootblock-y += bootblock.c
 
 romstage-$(CONFIG_CHROMEOS) += chromeos.c
+romstage-y += romstage.c
 
 ramstage-$(CONFIG_CHROMEOS) += chromeos.c
 ramstage-y += ec.c
diff --git a/src/mainboard/google/volteer/romstage.c b/src/mainboard/google/volteer/romstage.c
new file mode 100644
index 0000000000..7e87a2ad78
--- /dev/null
+++ b/src/mainboard/google/volteer/romstage.c
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2020 The coreboot project Authors.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include <baseboard/variants.h>
+#include <gpio.h>
+#include <soc/gpio.h>
+#include <soc/meminit_tgl.h>
+#include <soc/romstage.h>
+#include <variant/gpio.h>
+
+#include <fsp/soc_binding.h>
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig;
+	const struct mb_lpddr4x_cfg *board_cfg = variant_memory_params();
+	const struct spd_info spd_info = {
+		.read_type = READ_SPD_CBFS,
+		.spd_spec.spd_index = variant_memory_sku(),
+	};
+	bool half_populated = gpio_get(GPIO_MEM_CH_SEL);
+
+	meminit_lpddr4x_dimm0(mem_cfg, board_cfg, &spd_info, half_populated);
+}
diff --git a/src/mainboard/google/volteer/variants/baseboard/Makefile.inc b/src/mainboard/google/volteer/variants/baseboard/Makefile.inc
index 30f2b4605a..87a8667bc6 100644
--- a/src/mainboard/google/volteer/variants/baseboard/Makefile.inc
+++ b/src/mainboard/google/volteer/variants/baseboard/Makefile.inc
@@ -8,6 +8,8 @@
 
 bootblock-y += gpio.c
 
+romstage-y += memory.c
+
 ramstage-y += gpio.c
 
 smm-y += gpio.c
diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h
index df4368bb0e..3f8597f9f4 100644
--- a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h
@@ -10,6 +10,7 @@
 #define __BASEBOARD_VARIANTS_H__
 
 #include <soc/gpio.h>
+#include <soc/meminit_tgl.h>
 #include <stddef.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
@@ -23,6 +24,7 @@ const struct pad_config *variant_override_gpio_table(size_t *num);
 
 const struct cros_gpio *variant_cros_gpios(size_t *num);
 
+const struct mb_lpddr4x_cfg *variant_memory_params(void);
 int variant_memory_sku(void);
 
 #endif /* __BASEBOARD_VARIANTS_H__ */
diff --git a/src/mainboard/google/volteer/variants/baseboard/memory.c b/src/mainboard/google/volteer/variants/baseboard/memory.c
new file mode 100644
index 0000000000..111719871d
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/baseboard/memory.c
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2020 The coreboot project Authors.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <gpio.h>
+
+static const struct mb_lpddr4x_cfg baseboard_memcfg = {
+	/* DQ byte map */
+	.dq_map = {
+	{  0,  1,  2,  3,  4,  5,  6,  7,   /* Byte 0 */
+	  12, 13, 14, 15, 11, 10,  9,  8 }, /* Byte 1 */
+	{  7,  2,  6,  3,  5,  1,  4,  0,   /* Byte 2 */
+	  10,  8,  9, 11, 15, 12, 14, 13 }, /* Byte 3 */
+	{  3,  2,  1,  0,  4,  5,  6,  7,   /* Byte 4 */
+	  12, 13, 14, 15, 11, 10,  9,  8 }, /* Byte 5 */
+	{  7,  0,  1,  6,  5,  4,  2,  3,   /* Byte 6 */
+	  15, 14,  8,  9, 10, 12, 11, 13 }, /* Byte 7 */
+	{  3,  2,  1,  0,  4,  5,  6,  7,   /* Byte 0 */
+	  12, 13, 14, 15, 11, 10,  9,  8 }, /* Byte 1 */
+	{  3,  4,  2,  5,  0,  6,  1,  7,   /* Byte 2 */
+	  13, 12, 11, 10, 14, 15,  9,  8 }, /* Byte 3 */
+	{  3,  2,  1,  0,  7,  4,  5,  6,   /* Byte 4 */
+	  15, 14, 13, 12,  8,  9, 10, 11 }, /* Byte 5 */
+	{  3,  4,  2,  5,  1,  0,  7,  6,   /* Byte 6 */
+	  15, 14,  9,  8, 12, 10, 11, 13 }  /* Byte 7 */
+	},
+
+	/* DQS CPU<>DRAM map */
+	.dqs_map = {
+	/* Ch 0     1         2         3 */
+	{ 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 },
+	{ 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }
+	},
+
+	.ect = 0, /* Disable Early Command Training */
+};
+
+const struct mb_lpddr4x_cfg *__weak variant_memory_params(void)
+{
+	return &baseboard_memcfg;
+}
+
+int __weak variant_memory_sku(void)
+{
+	gpio_t spd_gpios[] = {
+		GPIO_MEM_CONFIG_0,
+		GPIO_MEM_CONFIG_1,
+		GPIO_MEM_CONFIG_2,
+		GPIO_MEM_CONFIG_3,
+	};
+
+	return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
+}