nyan*: Add fast link training functions
Some panels (including those on Big DVT) cannot work fine without link training
before sending the video signals, especially multi-lane Full HD panels. We need
to use the fast link training functions from kernel to support them.
BRANCH=Nyan
BUG=chrome-os-partner:28128, chrome-os-partner:28129
TEST=tested on nyan, nyan_big dvt.
Vince verified on Full HD panels.
Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Change-Id: Ifde8daf0ebdc6fb407610d3563f3311b2a72dbc4
Original-Reviewed-on: https://chromium-review.googlesource.com/196162
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Original-Commit-Queue: Hung-Te Lin <hungte@chromium.org>
Original-Tested-by: Hung-Te Lin <hungte@chromium.org>
(cherry picked from commit 992132ff3431fc7abba10cc8e910e36d4f3a3f7a)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I5ed091ae7a872fd674ab21f9f80267052fcd24b1
Reviewed-on: http://review.coreboot.org/7864
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Jimmy Zhang
Marc Jones
parent
8548a4888a
commit
75f701799a
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@ -88,7 +88,7 @@ chip soc/nvidia/tegra124
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register "link_bw" = "10"
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# "10" is defined as SOR_LINK_SPEED_G2_7 in sor.h
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register "drive_current" = "0x13131313"
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register "preemphasis" = "0x00000000"
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register "drive_current" = "0x40404040"
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register "preemphasis" = "0x0f0f0f0f"
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register "postcursor" = "0"
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end
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@ -88,7 +88,7 @@ chip soc/nvidia/tegra124
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register "link_bw" = "10"
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# "10" is defined as SOR_LINK_SPEED_G2_7 in sor.h
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register "drive_current" = "0x13131313"
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register "preemphasis" = "0x00000000"
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register "drive_current" = "0x40404040"
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register "preemphasis" = "0x0f0f0f0f"
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register "postcursor" = "0"
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end
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@ -88,7 +88,7 @@ chip soc/nvidia/tegra124
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register "link_bw" = "10"
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# "10" is defined as SOR_LINK_SPEED_G2_7 in sor.h
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register "drive_current" = "0x13131313"
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register "preemphasis" = "0x00000000"
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register "drive_current" = "0x40404040"
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register "preemphasis" = "0x0f0f0f0f"
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register "postcursor" = "0"
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end
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@ -291,6 +291,34 @@ static int tegra_dc_dpaux_read_chunk(struct tegra_dc_dp_data *dp, u32 cmd,
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return -1;
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}
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static int tegra_dc_dpaux_read(struct tegra_dc_dp_data *dp, u32 cmd, u32 addr,
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u8 *data, u32 *size, u32 *aux_stat)
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{
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u32 finished = 0;
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u32 cur_size;
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int ret = 0;
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do {
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cur_size = *size - finished;
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if (cur_size > DP_AUX_MAX_BYTES)
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cur_size = DP_AUX_MAX_BYTES;
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ret = tegra_dc_dpaux_read_chunk(dp, cmd, addr,
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data, &cur_size, aux_stat);
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if (ret)
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break;
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/* cur_size should be the real size returned */
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addr += cur_size;
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data += cur_size;
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finished += cur_size;
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} while (*size > finished);
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*size = finished;
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return ret;
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}
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static int tegra_dc_dp_dpcd_read(struct tegra_dc_dp_data *dp, u32 cmd,
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u8 * data_ptr)
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{
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@ -413,7 +441,7 @@ static void tegra_dc_dp_dump_link_cfg(struct tegra_dc_dp_data *dp,
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link_cfg->hblank_sym);
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printk(BIOS_INFO, " vblank_sym %d\n",
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link_cfg->vblank_sym);
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};
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}
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/* Calcuate if given cfg can meet the mode request. */
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/* Return true if mode is possible, false otherwise. */
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@ -585,7 +613,7 @@ static int tegra_dc_dp_calc_config(struct tegra_dc_dp_data *dp,
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return 0;
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}
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static int tegra_dc_dp_init_link_cfg(
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static int tegra_dc_dp_init_max_link_cfg(
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struct soc_nvidia_tegra124_config *config,
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struct tegra_dc_dp_data *dp,
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struct tegra_dc_dp_link_config *link_cfg)
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@ -593,13 +621,31 @@ static int tegra_dc_dp_init_link_cfg(
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u8 dpcd_data;
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int ret;
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link_cfg->max_lane_count = config->lane_count;
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link_cfg->support_enhanced_framing = config->enhanced_framing;
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link_cfg->max_link_bw = config->link_bw;
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CHECK_RET(tegra_dc_dp_dpcd_read(dp, NV_DPCD_MAX_LANE_COUNT,
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&dpcd_data));
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link_cfg->max_lane_count = dpcd_data & NV_DPCD_MAX_LANE_COUNT_MASK;
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link_cfg->support_enhanced_framing =
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(dpcd_data & NV_DPCD_MAX_LANE_COUNT_ENHANCED_FRAMING_YES) ?
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1 : 0;
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CHECK_RET(tegra_dc_dp_dpcd_read(dp, NV_DPCD_MAX_DOWNSPREAD,
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&dpcd_data));
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link_cfg->downspread = (dpcd_data & NV_DPCD_MAX_DOWNSPREAD_VAL_0_5_PCT)?
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1 : 0;
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CHECK_RET(tegra_dc_dp_dpcd_read(dp, NV_DPCD_MAX_LINK_BANDWIDTH,
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&link_cfg->max_link_bw));
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link_cfg->bits_per_pixel = config->panel_bits_per_pixel;
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/*
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* Set to a high value for link training and attach.
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* Will be re-programmed when dp is enabled.
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*/
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link_cfg->drive_current = config->drive_current;
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link_cfg->preemphasis = config->preemphasis;
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link_cfg->postcursor = config->postcursor;
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link_cfg->bits_per_pixel = config->panel_bits_per_pixel;
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CHECK_RET(tegra_dc_dp_dpcd_read(dp, NV_DPCD_EDP_CONFIG_CAP,
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&dpcd_data));
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@ -634,6 +680,240 @@ static int tegra_dc_dp_set_assr(struct tegra_dc_dp_data *dp, int ena)
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return 0;
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}
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static int tegra_dp_set_link_bandwidth(struct tegra_dc_dp_data *dp, u8 link_bw)
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{
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tegra_dc_sor_set_link_bandwidth(&dp->sor, link_bw);
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/* Sink side */
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return tegra_dc_dp_dpcd_write(dp, NV_DPCD_LINK_BANDWIDTH_SET, link_bw);
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}
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static int tegra_dp_set_lane_count(struct tegra_dc_dp_data *dp,
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const struct tegra_dc_dp_link_config *link_cfg)
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{
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u8 dpcd_data;
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int ret;
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/* check if panel support enhanched_framing */
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dpcd_data = link_cfg->lane_count;
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if (link_cfg->enhanced_framing)
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dpcd_data |= NV_DPCD_LANE_COUNT_SET_ENHANCEDFRAMING_T;
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CHECK_RET(tegra_dc_dp_dpcd_write(dp, NV_DPCD_LANE_COUNT_SET,
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dpcd_data));
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tegra_dc_sor_set_lane_count(&dp->sor, link_cfg->lane_count);
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/* Also power down lanes that will not be used */
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return 0;
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}
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static int tegra_dc_dp_link_trained(struct tegra_dc_dp_data *dp,
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const struct tegra_dc_dp_link_config *cfg)
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{
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u32 lane;
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u8 mask;
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u8 data;
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int ret;
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for (lane = 0; lane < cfg->lane_count; ++lane) {
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CHECK_RET(tegra_dc_dp_dpcd_read(dp, (lane/2) ?
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NV_DPCD_LANE2_3_STATUS : NV_DPCD_LANE0_1_STATUS,
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&data));
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mask = (lane & 1) ?
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NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_YES |
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NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_YES |
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NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_YES :
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NV_DPCD_STATUS_LANEX_CR_DONE_YES |
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NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_YES |
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NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_YES;
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if ((data & mask) != mask)
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return -1;
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}
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return 0;
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}
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/*
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* All link training functions are ported from kernel dc driver.
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* See more details at drivers/video/tegra/dc/dp.c
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*/
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static int tegra_dc_dp_fast_link_training(struct tegra_dc_dp_data *dp,
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const struct tegra_dc_dp_link_config *link_cfg)
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{
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struct tegra_dc_sor_data *sor = &dp->sor;
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u8 link_bw;
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u8 lane_count;
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u16 data16;
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u32 data32;
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u32 size;
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u32 status;
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int j;
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u32 mask = 0xffff >> ((4 - link_cfg->lane_count) * 4);
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tegra_dc_sor_set_lane_parm(sor, link_cfg);
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tegra_dc_dp_dpcd_write(dp, NV_DPCD_MAIN_LINK_CHANNEL_CODING_SET,
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NV_DPCD_MAIN_LINK_CHANNEL_CODING_SET_ANSI_8B10B);
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/* Send TP1 */
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tegra_dc_sor_set_dp_linkctl(sor, 1, training_pattern_1, link_cfg);
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tegra_dc_dp_dpcd_write(dp, NV_DPCD_TRAINING_PATTERN_SET,
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NV_DPCD_TRAINING_PATTERN_SET_TPS_TP1);
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for (j = 0; j < link_cfg->lane_count; ++j)
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tegra_dc_dp_dpcd_write(dp, NV_DPCD_TRAINING_LANE0_SET + j,
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0x24);
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udelay(520);
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size = sizeof(data16);
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tegra_dc_dpaux_read(dp, DPAUX_DP_AUXCTL_CMD_AUXRD,
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NV_DPCD_LANE0_1_STATUS, (u8 *)&data16, &size, &status);
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status = mask & 0x1111;
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if ((data16 & status) != status) {
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printk(BIOS_ERR,
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"dp: Link training error for TP1 (%#x)\n", data16);
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return -EFAULT;
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}
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/* enable ASSR */
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tegra_dc_dp_set_assr(dp, link_cfg->scramble_ena);
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tegra_dc_sor_set_dp_linkctl(sor, 1, training_pattern_3, link_cfg);
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tegra_dc_dp_dpcd_write(dp, NV_DPCD_TRAINING_PATTERN_SET,
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link_cfg->link_bw == 20 ? 0x23 : 0x22);
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for (j = 0; j < link_cfg->lane_count; ++j)
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tegra_dc_dp_dpcd_write(dp, NV_DPCD_TRAINING_LANE0_SET + j,
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0x24);
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udelay(520);
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size = sizeof(data32);
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tegra_dc_dpaux_read(dp, DPAUX_DP_AUXCTL_CMD_AUXRD,
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NV_DPCD_LANE0_1_STATUS, (u8 *)&data32, &size, &status);
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if ((data32 & mask) != (0x7777 & mask)) {
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printk(BIOS_ERR,
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"dp: Link training error for TP2/3 (0x%x)\n", data32);
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return -EFAULT;
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}
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tegra_dc_sor_set_dp_linkctl(sor, 1, training_pattern_disabled,
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link_cfg);
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tegra_dc_dp_dpcd_write(dp, NV_DPCD_TRAINING_PATTERN_SET, 0);
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if (tegra_dc_dp_link_trained(dp, link_cfg)) {
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tegra_dc_sor_read_link_config(&dp->sor, &link_bw,
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&lane_count);
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printk(BIOS_ERR,
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"Fast link trainging failed, link bw %d, lane # %d\n",
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link_bw, lane_count);
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return -EFAULT;
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}
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printk(BIOS_INFO,
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"Fast link trainging succeeded, link bw %d, lane %d\n",
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link_cfg->link_bw, link_cfg->lane_count);
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return 0;
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}
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static int tegra_dp_link_config(struct tegra_dc_dp_data *dp,
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const struct tegra_dc_dp_link_config *link_cfg)
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{
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u8 dpcd_data;
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u8 link_bw;
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u8 lane_count;
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u32 retry;
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int ret;
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if (link_cfg->lane_count == 0) {
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printk(BIOS_ERR, "dp: error: lane count is 0. "
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"Can not set link config.\n");
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return -1;
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}
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/* Set power state if it is not in normal level */
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CHECK_RET(tegra_dc_dp_dpcd_read(dp, NV_DPCD_SET_POWER, &dpcd_data));
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if (dpcd_data == NV_DPCD_SET_POWER_VAL_D3_PWRDWN) {
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dpcd_data = NV_DPCD_SET_POWER_VAL_D0_NORMAL;
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retry = 3; /* DP spec requires 3 retries */
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do {
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ret = tegra_dc_dp_dpcd_write(dp,
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NV_DPCD_SET_POWER, dpcd_data);
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} while ((--retry > 0) && ret);
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if (ret) {
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printk(BIOS_ERR,
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"dp: Failed to set DP panel power\n");
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return ret;
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}
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}
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/* Enable ASSR if possible */
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if (link_cfg->alt_scramber_reset_cap)
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CHECK_RET(tegra_dc_dp_set_assr(dp, 1));
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ret = tegra_dp_set_link_bandwidth(dp, link_cfg->link_bw);
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if (ret) {
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printk(BIOS_ERR, "dp: Failed to set link bandwidth\n");
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return ret;
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}
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ret = tegra_dp_set_lane_count(dp, link_cfg);
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if (ret) {
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printk(BIOS_ERR, "dp: Failed to set lane count\n");
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return ret;
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}
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tegra_dc_sor_set_dp_linkctl(&dp->sor, 1, training_pattern_none,
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link_cfg);
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/* Now do the fast link training for eDP */
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ret = tegra_dc_dp_fast_link_training(dp, link_cfg);
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if (ret) {
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printk(BIOS_ERR, "dp: fast link training failed\n");
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return ret;
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}
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/* Everything goes well, double check the link config */
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/* TODO: record edc/c2 data for debugging */
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tegra_dc_sor_read_link_config(&dp->sor, &link_bw, &lane_count);
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if ((link_cfg->link_bw == link_bw) &&
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(link_cfg->lane_count == lane_count))
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return 0;
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else
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return -EFAULT;
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}
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static int tegra_dc_dp_explore_link_cfg(struct tegra_dc_dp_data *dp,
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struct tegra_dc_dp_link_config *link_cfg,
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const struct soc_nvidia_tegra124_config *config)
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{
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struct tegra_dc_dp_link_config temp_cfg;
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if (!config->pixel_clock || !config->xres || !config->yres) {
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printk(BIOS_ERR,
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"dp: error mode configuration");
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return -EINVAL;
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}
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if (!link_cfg->max_link_bw || !link_cfg->max_lane_count) {
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printk(BIOS_ERR,
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"dp: error link configuration");
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return -EINVAL;
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}
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link_cfg->is_valid = 0;
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memcpy(&temp_cfg, link_cfg, sizeof(temp_cfg));
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temp_cfg.link_bw = temp_cfg.max_link_bw;
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temp_cfg.lane_count = temp_cfg.max_lane_count;
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/*
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* set to max link config
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*/
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if ((!tegra_dc_dp_calc_config(dp, config, &temp_cfg)) &&
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(!(tegra_dp_link_config(dp, &temp_cfg))))
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/* the max link cfg is doable */
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memcpy(link_cfg, &temp_cfg, sizeof(temp_cfg));
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return link_cfg->is_valid ? 0 : -EFAULT;
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}
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static void tegra_dp_update_config(struct tegra_dc_dp_data *dp,
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struct soc_nvidia_tegra124_config *config)
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{
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@ -749,17 +1029,11 @@ void dp_enable(void * _dp)
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goto error_enable;
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}
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if (tegra_dc_dp_init_link_cfg(config, dp, &dp->link_cfg)) {
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if (tegra_dc_dp_init_max_link_cfg(config, dp, &dp->link_cfg)) {
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printk(BIOS_ERR, "dp: failed to init link configuration\n");
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goto error_enable;
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}
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/* enable ASSR */
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if (tegra_dc_dp_set_assr(dp, dp->link_cfg.scramble_ena)) {
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printk(BIOS_ERR, "dp: failed to enable ASSR\n");
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goto error_enable;
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}
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tegra_dc_sor_enable_dp(&dp->sor);
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tegra_dc_sor_set_panel_power(&dp->sor, 1);
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@ -790,6 +1064,11 @@ void dp_enable(void * _dp)
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printk(BIOS_ERR,
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"dp: failed to read the revision number from sink\n");
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if (tegra_dc_dp_explore_link_cfg(dp, &dp->link_cfg, config)) {
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printk(BIOS_ERR, "dp: error to configure link\n");
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goto error_enable;
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}
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tegra_dc_sor_set_power_state(&dp->sor, 1);
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tegra_dc_sor_attach(&dp->sor);
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