mb/google/kahlee: Enable 2T mode for liara
Liara auto restart issue is caused by memory access error and consequent kernel panic. To solve this issue, revert the CL:1243666 (Disable NbP-state on Liara) and use 2T mode instead. BUG=b:116082728 TEST=verify the 2T mode is enabled/boot into ChromeOS and no auto restart/run memtester passed 10 cycle. Change-Id: I3a96276d88ffb70530d72b15c07b59a01cc6209a Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
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@ -15,6 +15,7 @@
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#include <chip.h>
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#include <amdblocks/agesawrapper.h>
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#include <boardid.h>
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#define DIMMS_PER_CHANNEL 1
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#if DIMMS_PER_CHANNEL > MAX_DIMMS_PER_CH
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@ -34,12 +35,32 @@ static const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = {
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0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
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PSO_END
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};
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/* TODO: Remove when no longer needed */
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static const PSO_ENTRY DDR4LiaraMemoryConfiguration[] = {
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DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY),
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NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, DIMMS_PER_CHANNEL),
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NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, MAX_DRAM_CH),
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MOTHER_BOARD_LAYERS(LAYERS_6),
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MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL,
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0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
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CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
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ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
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CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL,
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0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
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TBLDRV_CONFIG_TO_OVERRIDE(DIMMS_PER_CHANNEL, ANY_SPEED, VOLT_ANY_,
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ANY_),
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TBLDRV_CONFIG_ENTRY_SLOWACCMODE(1),
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PSO_END
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};
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void OemPostParams(AMD_POST_PARAMS *PostParams)
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{
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PostParams->MemConfig.PlatformMemoryConfiguration =
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(PSO_ENTRY *)DDR4PlatformMemoryConfiguration;
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if ((IS_ENABLED(CONFIG_BOARD_GOOGLE_LIARA)) && (board_id() <= 4))
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PostParams->MemConfig.PlatformMemoryConfiguration =
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(PSO_ENTRY *)DDR4LiaraMemoryConfiguration;
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else
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PostParams->MemConfig.PlatformMemoryConfiguration =
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(PSO_ENTRY *)DDR4PlatformMemoryConfiguration;
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/*
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* Bank interleaving is enabled by default in AGESA. However, from AMD's
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* explanation, bank interleaving is really chip select interleave,
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@ -152,7 +152,4 @@ VOID __weak OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly)
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InitEarly->GnbConfig.PsppPolicy = PsppBalanceLow;
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InitEarly->PlatformConfig.GnbAzI2sBusSelect = GnbAcpI2sBus;
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InitEarly->PlatformConfig.GnbAzI2sBusPinConfig = GnbAcp2Tx4RxBluetooth;
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if ((IS_ENABLED(CONFIG_BOARD_GOOGLE_LIARA)) && (board_id() <= 4))
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InitEarly->PlatformConfig.PlatformProfile.NbPstatesSupported =
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FALSE;
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}
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