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mb/google/kahlee: Enable 2T mode for liara 

Liara auto restart issue is caused by memory access error and consequent
kernel panic. To solve this issue, revert the CL:1243666 (Disable
NbP-state on Liara) and use 2T mode instead.

BUG=b:116082728
TEST=verify the 2T mode is enabled/boot into ChromeOS and no auto restart/run
memtester passed 10 cycle.

Change-Id: I3a96276d88ffb70530d72b15c07b59a01cc6209a
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/29179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
This commit is contained in:
chris wang 2018-10-18 18:52:58 +08:00 committed by Martin Roth
parent d522db048b
commit 76118a7d19
2 changed files with 24 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

27
src/mainboard/google/kahlee/OemCustomize.c
View File

@ -15,6 +15,7 @@
#include <chip.h> #include <chip.h>
#include <amdblocks/agesawrapper.h> #include <amdblocks/agesawrapper.h>
#include <boardid.h>
#define DIMMS_PER_CHANNEL 1 #define DIMMS_PER_CHANNEL 1
#if DIMMS_PER_CHANNEL > MAX_DIMMS_PER_CH #if DIMMS_PER_CHANNEL > MAX_DIMMS_PER_CH
@ -34,12 +35,32 @@ static const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = {
0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00), 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
PSO_END PSO_END
}; };
/* TODO: Remove when no longer needed */
static const PSO_ENTRY DDR4LiaraMemoryConfiguration[] = {
DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY),
NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, DIMMS_PER_CHANNEL),
NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, MAX_DRAM_CH),
MOTHER_BOARD_LAYERS(LAYERS_6),
MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL,
0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL,
0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
TBLDRV_CONFIG_TO_OVERRIDE(DIMMS_PER_CHANNEL, ANY_SPEED, VOLT_ANY_,
ANY_),
TBLDRV_CONFIG_ENTRY_SLOWACCMODE(1),
PSO_END
};
void OemPostParams(AMD_POST_PARAMS *PostParams) void OemPostParams(AMD_POST_PARAMS *PostParams)
{ {
PostParams->MemConfig.PlatformMemoryConfiguration = if ((IS_ENABLED(CONFIG_BOARD_GOOGLE_LIARA)) && (board_id() <= 4))
(PSO_ENTRY *)DDR4PlatformMemoryConfiguration; PostParams->MemConfig.PlatformMemoryConfiguration =
(PSO_ENTRY *)DDR4LiaraMemoryConfiguration;
else
PostParams->MemConfig.PlatformMemoryConfiguration =
(PSO_ENTRY *)DDR4PlatformMemoryConfiguration;
/* /*
* Bank interleaving is enabled by default in AGESA. However, from AMD's * Bank interleaving is enabled by default in AGESA. However, from AMD's
* explanation, bank interleaving is really chip select interleave, * explanation, bank interleaving is really chip select interleave,

3
src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c
View File

@ -152,7 +152,4 @@ VOID __weak OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly)
InitEarly->GnbConfig.PsppPolicy = PsppBalanceLow; InitEarly->GnbConfig.PsppPolicy = PsppBalanceLow;
InitEarly->PlatformConfig.GnbAzI2sBusSelect = GnbAcpI2sBus; InitEarly->PlatformConfig.GnbAzI2sBusSelect = GnbAcpI2sBus;
InitEarly->PlatformConfig.GnbAzI2sBusPinConfig = GnbAcp2Tx4RxBluetooth; InitEarly->PlatformConfig.GnbAzI2sBusPinConfig = GnbAcp2Tx4RxBluetooth;
if ((IS_ENABLED(CONFIG_BOARD_GOOGLE_LIARA)) && (board_id() <= 4))
InitEarly->PlatformConfig.PlatformProfile.NbPstatesSupported =
FALSE;
} }