vc/intel/fsp/fsp2_0/CPX-SP: upgrade to ww38 FSP release
Intel CPX-SP FSP ww38 release made some changes to FSP-M header file. Those changes do not need corresponding soc code change. TESTED=built image with ww38 FSP RELEASE binary, booted DeltaLake DVT to target OS. Change-Id: I320c4a674f9f4d37c30ce6df510f18ad1ae057eb Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Jonathan Zhang
Patrick Georgi
parent
58a706af96
commit
7614099b8e
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@ -167,542 +167,552 @@ typedef struct {
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**/
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UINT8 SnoopThrottleConfig;
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/** Offset 0x006A - Legacy VGA Soc
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/** Offset 0x006A - Snoop Throttle Config
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Set the Snoop All Core Config
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0:DIS, 1:EN, 2:Auto
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**/
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UINT8 SnoopAllCores;
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/** Offset 0x006B - Legacy VGA Soc
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Socket that claims the legacy VGA range
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**/
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UINT8 LegacyVgaSoc;
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/** Offset 0x006B - Legacy VGA Stack
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/** Offset 0x006C - Legacy VGA Stack
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Stack that claims the legacy VGA range
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**/
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UINT8 LegacyVgaStack;
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/** Offset 0x006C - Pcie P2P Performance Mode
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/** Offset 0x006D - Pcie P2P Performance Mode
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Determine if to enable PCIe P2P Performance Mode
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$EN_DIS
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**/
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UINT8 P2pRelaxedOrdering;
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/** Offset 0x006D - Debug Print Level
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/** Offset 0x006E - Debug Print Level
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Set Debug Print Level
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1:Fatal, 2:Warning, 4:Summary, 8:Detail, 0x0F:All
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**/
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UINT8 DebugPrintLevel;
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/** Offset 0x006E - SNC
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/** Offset 0x006F - SNC
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Enable or Disable SNC
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$EN_DIS
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**/
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UINT8 SncEn;
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/** Offset 0x006F - UMA Clustering
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/** Offset 0x0070 - UMA Clustering
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Set UMA Clusters
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0:Disable, 2:Two Clusters, 4:Four Clusters
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**/
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UINT8 UmaClustering;
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/** Offset 0x0070 - IODC Mode
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/** Offset 0x0071 - IODC Mode
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IODC Setup Option
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0:Disable, 1:Auto, 2:Push, 3:AllocFlow 4:NonAlloc, 5:WCILF
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**/
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UINT8 IoDcMode;
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/** Offset 0x0071 - Degrade Precedence
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/** Offset 0x0072 - Degrade Precedence
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Setup Degrade Precedence
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0:Topology, 1:Feature
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**/
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UINT8 DegradePrecedence;
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/** Offset 0x0072 - Degrade 4 Socket Preference
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/** Offset 0x0073 - Degrade 4 Socket Preference
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Setup Degrade 4 Socket Preference
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0:Fully Connect, 1:Dual Link Ring
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**/
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UINT8 Degrade4SPreference;
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/** Offset 0x0073 - Directory Mode
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/** Offset 0x0074 - Directory Mode
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Enable or Disable Directory Mode
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$EN_DIS
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**/
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UINT8 DirectoryModeEn;
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/** Offset 0x0074 - XPT Prefetch Enable
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/** Offset 0x0075 - XPT Prefetch Enable
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Enable or Disable XPT Prefetch
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**/
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UINT8 XptPrefetchEn;
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/** Offset 0x0075 - KTI Prefetch Enable
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/** Offset 0x0076 - KTI Prefetch Enable
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Enable or Disable KTI Prefetch
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$EN_DIS
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**/
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UINT8 KtiPrefetchEn;
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/** Offset 0x0076 - XPT Remote Prefetch Enable
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/** Offset 0x0077 - XPT Remote Prefetch Enable
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Enable or Disable XPT Remote Prefetch Enable
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$EN_DIS
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**/
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UINT8 XptRemotePrefetchEn;
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/** Offset 0x0077 - KTI FPGA
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/** Offset 0x0078 - KTI FPGA
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Enable or Disable KTI FPGA
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$EN_DIS
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**/
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UINT8 KtiFpgaEnable[8];
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/** Offset 0x007F - DDRT QoS Mode
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/** Offset 0x0080 - DDRT QoS Mode
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Setup DDRT QoS
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**/
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UINT8 DdrtQosMode;
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/** Offset 0x0080 - KTI Link Speed Mode
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/** Offset 0x0081 - KTI Link Speed Mode
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Choose KTI Link Speed Mode
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**/
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UINT8 KtiLinkSpeedMode;
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/** Offset 0x0081 - KTI Link Speed
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/** Offset 0x0082 - KTI Link Speed
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Setup KTI Link Speed
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**/
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UINT8 KtiLinkSpeed;
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/** Offset 0x0082 - KTI Link L0p
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/** Offset 0x0083 - KTI Link L0p
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Enable or Disable KTI Link L0p
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**/
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UINT8 KtiLinkL0pEn;
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/** Offset 0x0083 - KTI Link L1
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/** Offset 0x0084 - KTI Link L1
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Enable or Disable KTI Link L1
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**/
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UINT8 KtiLinkL1En;
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/** Offset 0x0084 - KTI Failover
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/** Offset 0x0085 - KTI Failover
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Enable or Disable KTI Failover
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**/
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UINT8 KtiFailoverEn;
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/** Offset 0x0085 - KTI LB Enable
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/** Offset 0x0086 - KTI LB Enable
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Enable or Disable KTI LB
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$EN_DIS
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**/
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UINT8 KtiLbEn;
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/** Offset 0x0086 - KTI CRC Mode
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/** Offset 0x0087 - KTI CRC Mode
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Select KTI CRC Mode
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0:16bit, 1:32bit, 2:Auto
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**/
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UINT8 KtiCrcMode;
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/** Offset 0x0087 - KTI CPU Socket Hotplug
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/** Offset 0x0088 - KTI CPU Socket Hotplug
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Enable or Disable KTI CPU Socket Hotplug
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$EN_DIS
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**/
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UINT8 KtiCpuSktHotPlugEn;
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/** Offset 0x0088 - KTI CPU Socket HotPlug Topology
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/** Offset 0x0089 - KTI CPU Socket HotPlug Topology
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Select KTI CPU Socket HotPlug Topology
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0:4Socket, 1:8Socket
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**/
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UINT8 KtiCpuSktHotPlugTopology;
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/** Offset 0x0089 - KTI SKU Mismatch Check
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/** Offset 0x008A - KTI SKU Mismatch Check
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Enable or Disable KTI SKU Mismatch Check
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$EN_DIS
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**/
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UINT8 KtiSkuMismatchCheck;
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/** Offset 0x008A - IRQ Threshold
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/** Offset 0x008B - IRQ Threshold
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Select IRQ Threshold
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0:Disable, 1:Auto, 2:Low, 3:Medium, 4:High
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**/
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UINT8 IrqThreshold;
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/** Offset 0x008B - IRQ Threshold
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/** Offset 0x008C - IRQ Threshold
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Enable or Disable
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0:Disable, 1:Auto, 2:Low, 3:Medium, 4:High
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**/
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UINT8 TorThresLoctoremNorm;
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/** Offset 0x008C - TOR threshold - Loctorem threshold empty
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/** Offset 0x008D - TOR threshold - Loctorem threshold empty
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Select TOR threshold - Loctorem threshold empty
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0:Disable, 1:Auto, 2:Low, 3:Medium, 4:High
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**/
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UINT8 TorThresLoctoremEmpty;
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/** Offset 0x008D - MBA BW Calibration
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/** Offset 0x008E - MBA BW Calibration
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MBA BW Calibration setting
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0:Linear, 1:Biased, 2:Legacy, 3:Auto
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**/
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UINT8 MbeBwCal;
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/** Offset 0x008E - TSC Sync in Sockets
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/** Offset 0x008F - TSC Sync in Sockets
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Enable or Disable TSC Sync in Sockets
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**/
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UINT8 TscSyncEn;
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/** Offset 0x008F - HA A to S directory optimization
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/** Offset 0x0090 - HA A to S directory optimization
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Enable or Disable HA A to S directory optimization
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**/
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UINT8 StaleAtoSOptEn;
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/** Offset 0x0090 - LLC Deadline Allocation
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/** Offset 0x0091 - LLC Deadline Allocation
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Enable or Disable LLC Deadline Allocation
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$EN_DIS
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**/
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UINT8 LLCDeadLineAlloc;
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/** Offset 0x0091 - Split Lock
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/** Offset 0x0092 - Split Lock
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Enable or Disable Split Lock
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**/
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UINT8 SplitLock;
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/** Offset 0x0092 - MMCFG Base Address
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/** Offset 0x0093 - MMCFG Base Address
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Setup MMCFG Base Address
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0:1G, 1:1.5G, 2:1.75G, 3:2G, 4:2.25G, 5:3G, 6:Auto
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**/
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UINT8 mmCfgBase;
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/** Offset 0x0093 - MMCFG Size
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/** Offset 0x0094 - MMCFG Size
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Select MMCFG Size
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0:64M, 1:128M, 2:256M, 3:512M, 4:1G, 5:2G, 6: Auto
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**/
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UINT8 mmCfgSize;
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/** Offset 0x0094 - MMIO High Base Address
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/** Offset 0x0095
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**/
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UINT8 UnusedUpdSpace0[3];
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/** Offset 0x0098 - MMIO High Base Address
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MMIO High Base Address, a hex number for Bit[51:32]
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**/
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UINT32 mmiohBase;
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/** Offset 0x0098 - CPU Physical Address Limit
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/** Offset 0x009C - CPU Physical Address Limit
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CPU Physical Address Limit
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0:Disable, 1:Enable
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**/
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UINT8 CpuPaLimit;
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/** Offset 0x0099 - High Gap
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/** Offset 0x009D - High Gap
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Enable or Disable High Gap
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$EN_DIS
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**/
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UINT8 highGap;
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/** Offset 0x009A - MMIO High Size
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/** Offset 0x009E - MMIO High Size
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MMIO High Size, Number of 1GB contiguous regions to be assigned for MMIOH space
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per CPU. Range 1-1024
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**/
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UINT16 mmiohSize;
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/** Offset 0x009C - } TYPE:{Combo
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/** Offset 0x00A0 - } TYPE:{Combo
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Enable or Disable
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$EN_DIS
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**/
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UINT8 isocEn;
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/** Offset 0x009D - DCA
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/** Offset 0x00A1 - DCA
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Enable or Disable DCA
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$EN_DIS
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**/
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UINT8 dcaEn;
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/** Offset 0x009E
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/** Offset 0x00A2
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**/
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UINT8 UnusedUpdSpace0[2];
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/** Offset 0x00A0 - } TYPE:{Combo
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Enable or Disable
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$EN_DIS
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**/
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UINT32 BoardTypeBitmask;
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UINT8 UnusedUpdSpace1[2];
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/** Offset 0x00A4 - } TYPE:{Combo
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Enable or Disable
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$EN_DIS
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**/
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UINT32 AllLanesPtr;
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UINT32 BoardTypeBitmask;
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/** Offset 0x00A8 - } TYPE:{Combo
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Enable or Disable
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$EN_DIS
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**/
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UINT32 PerLanePtr;
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UINT32 AllLanesPtr;
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/** Offset 0x00AC - } TYPE:{Combo
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Enable or Disable
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$EN_DIS
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**/
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UINT32 AllLanesSizeOfTable;
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UINT32 PerLanePtr;
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/** Offset 0x00B0 - } TYPE:{Combo
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Enable or Disable
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$EN_DIS
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**/
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UINT32 PerLaneSizeOfTable;
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UINT32 AllLanesSizeOfTable;
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/** Offset 0x00B4 - } TYPE:{Combo
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Enable or Disable
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$EN_DIS
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**/
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UINT32 WaitTimeForPSBP;
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UINT32 PerLaneSizeOfTable;
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/** Offset 0x00B8 - } TYPE:{Combo
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Enable or Disable
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$EN_DIS
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**/
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UINT32 WaitTimeForPSBP;
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/** Offset 0x00BC - } TYPE:{Combo
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Enable or Disable
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$EN_DIS
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**/
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UINT8 IsKtiNvramDataReady;
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/** Offset 0x00B9 - } TYPE:{Combo
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/** Offset 0x00BD - } TYPE:{Combo
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Enable or Disable
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$EN_DIS
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**/
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UINT8 BoardId;
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/** Offset 0x00BA - } TYPE:{Combo
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/** Offset 0x00BE - } TYPE:{Combo
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Enable or Disable
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$EN_DIS
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**/
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UINT8 WaSerializationEn;
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/** Offset 0x00BB - } TYPE:{Combo
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/** Offset 0x00BF - } TYPE:{Combo
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Enable or Disable
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$EN_DIS
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**/
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UINT8 KtiInEnableMktme;
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/** Offset 0x00BC - Usage type for Processor VmxEnable Function
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/** Offset 0x00C0 - Usage type for Processor VmxEnable Function
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Processor VmxEnable Function, if enabled, the value is 0x01, if disabled, the value is 0x00
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$EN_DIS
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**/
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UINT8 VmxEnable;
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/** Offset 0x00BD - Usage type for Processor X2apic Function
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/** Offset 0x00C1 - Usage type for Processor X2apic Function
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Processor X2apic Function, if enabled, the value is 0x01, if disabled, the value is 0x00
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**/
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UINT8 X2apic;
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/** Offset 0x00BE - Usage type for DDR frequency limit
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/** Offset 0x00C2 - Usage type for DDR frequency limit
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Processor X2apic Function, if enabled, the value is 0x01, if disabled, the value is 0x00
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**/
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UINT8 DdrFreqLimit;
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/** Offset 0x00BF - Usage type for Memory Serial Debug Message Level
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/** Offset 0x00C3 - Usage type for Memory Serial Debug Message Level
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Processor X2apic Function, if enabled, the value is 0x01, if disabled, the value is 0x00
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**/
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UINT8 serialDebugMsgLvl;
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/** Offset 0x00C0 - IIO ConfigIOU0
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/** Offset 0x00C4 - IIO ConfigIOU0
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ConfigIOU[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
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0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO
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**/
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UINT8 IioConfigIOU0[8];
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/** Offset 0x00C8 - IIO ConfigIOU1
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/** Offset 0x00CC - IIO ConfigIOU1
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ConfigIOU[MAX_SOCKET][1]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
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0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO
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**/
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UINT8 IioConfigIOU1[8];
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/** Offset 0x00D0 - IIO ConfigIOU2
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/** Offset 0x00D4 - IIO ConfigIOU2
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ConfigIOU[MAX_SOCKET][2]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
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0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO
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**/
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UINT8 IioConfigIOU2[8];
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/** Offset 0x00D8 - IIO ConfigIOU3
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/** Offset 0x00DC - IIO ConfigIOU3
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ConfigIOU[MAX_SOCKET][3]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
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0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO
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**/
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UINT8 IioConfigIOU3[8];
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/** Offset 0x00E0 - IIO ConfigIOU4
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/** Offset 0x00E4 - IIO ConfigIOU4
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ConfigIOU[MAX_SOCKET][4]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
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0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO
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**/
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UINT8 IioConfigIOU4[8];
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/** Offset 0x00E8 - Usage type for IIO PCIE Config Table Ptr
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/** Offset 0x00EC - Usage type for IIO PCIE Config Table Ptr
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IIO PCIE Config Table Ptr
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**/
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UINT32 IioPcieConfigTablePtr;
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/** Offset 0x00EC - Usage type for IIO PCIE Config Table Number
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/** Offset 0x00F0 - Usage type for IIO PCIE Config Table Number
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IIO PCIE Config Table Number
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**/
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UINT32 IioPcieConfigTableNumber;
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/** Offset 0x00F0 - Usage type for IIO PCIE Root Port Enable or Disable
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/** Offset 0x00F4 - Usage type for IIO PCIE Root Port Enable or Disable
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IIO PCH rootport, if port is enabled, the value is 0x01, if the port is disabled,
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the value is 0x00
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**/
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UINT8 IIOPcieRootPortEnable;
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/** Offset 0x00F1 - Usage type for IIO DeEmphasis
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/** Offset 0x00F5 - Usage type for IIO DeEmphasis
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IIO DeEmphasis
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**/
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UINT8 DeEmphasis;
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/** Offset 0x00F2 - Usage type for IIO PCIE Root Port link speed
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/** Offset 0x00F6 - Usage type for IIO PCIE Root Port link speed
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IIO root port link speed
|
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**/
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UINT8 IIOPciePortLinkSpeed;
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/** Offset 0x00F3 - Usage type for IIO PCIE Root Port Max Payload
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/** Offset 0x00F7 - Usage type for IIO PCIE Root Port Max Payload
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IIO Root Port Max Payload
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**/
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UINT8 IIOPcieMaxPayload;
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/** Offset 0x00F4 - Usage type for IIO DfxDnTxPreset
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/** Offset 0x00F8 - Usage type for IIO DfxDnTxPreset
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IIO DfxDnTxPreset
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**/
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UINT8 DfxDnTxPreset;
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/** Offset 0x00F5 - Usage type for IIO DfxRxPreset
|
||||
/** Offset 0x00F9 - Usage type for IIO DfxRxPreset
|
||||
IIO DfxRxPreset
|
||||
**/
|
||||
UINT8 DfxRxPreset;
|
||||
|
||||
/** Offset 0x00F6 - Usage type for IIO DfxUpTxPreset
|
||||
/** Offset 0x00FA - Usage type for IIO DfxUpTxPreset
|
||||
IIO DfxUpTxPreset
|
||||
**/
|
||||
UINT8 DfxUpTxPreset;
|
||||
|
||||
/** Offset 0x00F7 - Usage type for IIO PcieCommonClock
|
||||
/** Offset 0x00FB - Usage type for IIO PcieCommonClock
|
||||
IIO PcieCommonClock
|
||||
**/
|
||||
UINT8 PcieCommonClock;
|
||||
|
||||
/** Offset 0x00F8 - Usage type for IIO NtbPpd
|
||||
/** Offset 0x00FC - Usage type for IIO NtbPpd
|
||||
IIO NtbPpd
|
||||
**/
|
||||
UINT8 NtbPpd;
|
||||
|
||||
/** Offset 0x00F9 - Usage type for IIO NtbBarSizeOverride
|
||||
/** Offset 0x00FD - Usage type for IIO NtbBarSizeOverride
|
||||
IIO NtbBarSizeOverride
|
||||
**/
|
||||
UINT8 NtbBarSizeOverride;
|
||||
|
||||
/** Offset 0x00FA - Usage type for IIO NtbSplitBar
|
||||
/** Offset 0x00FE - Usage type for IIO NtbSplitBar
|
||||
IIO NtbSplitBar
|
||||
**/
|
||||
UINT8 NtbSplitBar;
|
||||
|
||||
/** Offset 0x00FB - Usage type for IIO NtbBarSizeImBar1
|
||||
/** Offset 0x00FF - Usage type for IIO NtbBarSizeImBar1
|
||||
IIO NtbBarSizeImBar1
|
||||
**/
|
||||
UINT8 NtbBarSizeImBar1;
|
||||
|
||||
/** Offset 0x00FC - Usage type for IIO NtbBarSizeImBar2
|
||||
/** Offset 0x0100 - Usage type for IIO NtbBarSizeImBar2
|
||||
IIO PNtbBarSizeImBar2
|
||||
**/
|
||||
UINT8 NtbBarSizeImBar2;
|
||||
|
||||
/** Offset 0x00FD - Usage type for IIO NtbBarSizeImBar2_0
|
||||
/** Offset 0x0101 - Usage type for IIO NtbBarSizeImBar2_0
|
||||
IIO PNtbBarSizeImBar2_0
|
||||
**/
|
||||
UINT8 NtbBarSizeImBar2_0;
|
||||
|
||||
/** Offset 0x00FE - Usage type for IIO NtbBarSizeImBar2_1
|
||||
/** Offset 0x0102 - Usage type for IIO NtbBarSizeImBar2_1
|
||||
IIO NtbBarSizeImBar2_1
|
||||
**/
|
||||
UINT8 NtbBarSizeImBar2_1;
|
||||
|
||||
/** Offset 0x00FF - Usage type for IIO NtbBarSizeEmBarSZ1
|
||||
/** Offset 0x0103 - Usage type for IIO NtbBarSizeEmBarSZ1
|
||||
IIO NtbBarSizeEmBarSZ1
|
||||
**/
|
||||
UINT8 NtbBarSizeEmBarSZ1;
|
||||
|
||||
/** Offset 0x0100 - Usage type for IIO NtbBarSizeEmBarSZ2
|
||||
/** Offset 0x0104 - Usage type for IIO NtbBarSizeEmBarSZ2
|
||||
IIO NtbBarSizeEmBarSZ2
|
||||
**/
|
||||
UINT8 NtbBarSizeEmBarSZ2;
|
||||
|
||||
/** Offset 0x0101 - Usage type for IIO NtbBarSizeEmBarSZ2_0
|
||||
/** Offset 0x0105 - Usage type for IIO NtbBarSizeEmBarSZ2_0
|
||||
IIO NtbBarSizeEmBarSZ2_0
|
||||
**/
|
||||
UINT8 NtbBarSizeEmBarSZ2_0;
|
||||
|
||||
/** Offset 0x0102 - Usage type for IIO NtbBarSizeEmBarSZ2_1
|
||||
/** Offset 0x0106 - Usage type for IIO NtbBarSizeEmBarSZ2_1
|
||||
IIO NtbBarSizeEmBarSZ2_1
|
||||
**/
|
||||
UINT8 NtbBarSizeEmBarSZ2_1;
|
||||
|
||||
/** Offset 0x0103 - Usage type for IIO NtbXlinkCtlOverride
|
||||
/** Offset 0x0107 - Usage type for IIO NtbXlinkCtlOverride
|
||||
IIO NtbXlinkCtlOverride
|
||||
**/
|
||||
UINT8 NtbXlinkCtlOverride;
|
||||
|
||||
/** Offset 0x0104 - Usage type for IIO VT-D Function
|
||||
/** Offset 0x0108 - Usage type for IIO VT-D Function
|
||||
IIO VT-D Function, if supported, the value is 0x01, if not supported, the value is 0x00
|
||||
**/
|
||||
UINT8 VtdSupport;
|
||||
|
||||
/** Offset 0x0105 - Usage type for IIO Pcie Port Hide
|
||||
/** Offset 0x0109 - Usage type for IIO Pcie Port Hide
|
||||
Hide or visible for IIO Pcie Port, 1 : Hide, 0 : Visible
|
||||
**/
|
||||
UINT8 PEXPHIDE;
|
||||
|
||||
/** Offset 0x0106 - Usage type for IIO Pcie Port Menu Hide
|
||||
/** Offset 0x010A - Usage type for IIO Pcie Port Menu Hide
|
||||
Hide or visible for IIO Pcie Port Menu, 1 : Hide, 0 : Visible
|
||||
**/
|
||||
UINT8 HidePEXPMenu;
|
||||
|
||||
/** Offset 0x0107 - PchSirqMode
|
||||
/** Offset 0x010B - PchSirqMode
|
||||
Enable or Disable PchSirqMode
|
||||
**/
|
||||
UINT8 PchSirqMode;
|
||||
|
||||
/** Offset 0x0108 - PchAdrEn
|
||||
/** Offset 0x010C - PchAdrEn
|
||||
Enable or Disable PchAdr
|
||||
**/
|
||||
UINT8 PchAdrEn;
|
||||
|
||||
/** Offset 0x0109 - ThermalDeviceEnable
|
||||
/** Offset 0x010D - ThermalDeviceEnable
|
||||
Enable or Disable ThermalDeviceEnable with PCI or ACPI mode
|
||||
**/
|
||||
UINT8 ThermalDeviceEnable;
|
||||
|
||||
/** Offset 0x010A - } TYPE:{Combo
|
||||
/** Offset 0x010E - } TYPE:{Combo
|
||||
Root port swapping based on device connection status : TRUE or FALSE
|
||||
TRUE : 0x01, FALSE : 0x00
|
||||
**/
|
||||
UINT8 PchPcieRootPortFunctionSwap;
|
||||
|
||||
/** Offset 0x010B - PCH PCIE PLL Ssc
|
||||
/** Offset 0x010F - PCH PCIE PLL Ssc
|
||||
Valid spread range : 0x00-0x14 (A value of 0 is SSC of 0.0%. A value of 20 is SSC
|
||||
of 2.0%), Auto : 0xFE(Set to hardware default), Disable : 0xFF
|
||||
**/
|
||||
UINT8 PchPciePllSsc;
|
||||
|
||||
/** Offset 0x010C - Usage type for PCH PCIE Root Port Index
|
||||
/** Offset 0x0110 - Usage type for PCH PCIE Root Port Index
|
||||
Index assigned to every PCH PCIE Root Port
|
||||
**/
|
||||
UINT8 PchPciePortIndex[20];
|
||||
|
||||
/** Offset 0x0120 - Usage type for PCH PCIE Root Port Enable or Disable
|
||||
/** Offset 0x0124 - Usage type for PCH PCIE Root Port Enable or Disable
|
||||
0-19: PCH rootport, if port is enabled, the value is 0x01, if the port is disabled,
|
||||
the value is 0x00
|
||||
**/
|
||||
UINT8 PchPcieForceEnable[20];
|
||||
|
||||
/** Offset 0x0134 - Usage type for PCH PCIE Root Port Link Speed
|
||||
/** Offset 0x0138 - Usage type for PCH PCIE Root Port Link Speed
|
||||
0-19: PCH rootport, 0x00 : Pcie Auto Speed, 0x01 : Pcie Gen1 Speed, 0x02 : Pcie
|
||||
Gen2 Speed, 0x03 : Pcie Gen3 Speed
|
||||
**/
|
||||
UINT8 PchPciePortLinkSpeed[20];
|
||||
|
||||
/** Offset 0x0148 - PchDciEn
|
||||
/** Offset 0x014C - PchDciEn
|
||||
Enable or Disable Pch DciEn
|
||||
**/
|
||||
UINT8 PchDciEn;
|
||||
|
||||
/** Offset 0x0149 - SerialIoUartDebugEnable
|
||||
/** Offset 0x014D - SerialIoUartDebugEnable
|
||||
Enable SerialIo Uart debug library in FSP.
|
||||
0:Disable, 1:Enable
|
||||
**/
|
||||
UINT8 SerialIoUartDebugEnable;
|
||||
|
||||
/** Offset 0x014A - ISA Serial Base selection
|
||||
/** Offset 0x014E - ISA Serial Base selection
|
||||
Select ISA Serial Base address could be initialized by boot loader. Default is 0x3F8
|
||||
0x3F8, 0x2F8
|
||||
**/
|
||||
UINT16 SerialIoUartDebugIoBase;
|
||||
|
||||
/** Offset 0x014C
|
||||
/** Offset 0x0150
|
||||
**/
|
||||
UINT8 ReservedMemoryInitUpd[16];
|
||||
} FSPM_CONFIG;
|
||||
|
|
@ -723,11 +733,11 @@ typedef struct {
|
|||
**/
|
||||
FSPM_CONFIG FspmConfig;
|
||||
|
||||
/** Offset 0x015C
|
||||
/** Offset 0x0160
|
||||
**/
|
||||
UINT8 UnusedUpdSpace1[2];
|
||||
UINT8 UnusedUpdSpace2[6];
|
||||
|
||||
/** Offset 0x015E
|
||||
/** Offset 0x0166
|
||||
**/
|
||||
UINT16 UpdTerminator;
|
||||
} FSPM_UPD;
|
||||
|
|
|
|||
|
|
@ -144,7 +144,7 @@ typedef struct SystemMemoryMapHob {
|
|||
UINT8 NumChPerMC;
|
||||
UINT8 numberEntries; // Number of Memory Map Elements
|
||||
SYSTEM_MEMORY_MAP_ELEMENT Element[(MAX_SOCKET * MAX_DRAM_CLUSTERS * MAX_SAD_RULES) + MAX_FPGA_REMOTE_SAD_RULES];
|
||||
UINT8 reserved3[2212];
|
||||
UINT8 reserved3[2213];
|
||||
MEMMAP_SOCKET Socket[MAX_SOCKET];
|
||||
UINT8 reserved4[1603];
|
||||
|
||||
|
|
@ -154,7 +154,7 @@ typedef struct SystemMemoryMapHob {
|
|||
|
||||
UINT32 MmiohBase; // MMIOH base in 64MB granularity
|
||||
|
||||
UINT8 reserved6[2];
|
||||
UINT8 reserved6[4];
|
||||
|
||||
} SYSTEM_MEMORY_MAP_HOB;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue