cpu/x86/Kconfig.debug_cpu: drop HAVE_DISPLAY_MTRRS option

Since all x86 CPUs in tree have MTRR support, there is no need to guard
the DISPLAY_MTRRS option with HAVE_DISPLAY_MTRRS. Also all x86 CPUs/SoCs
have a display_mtrrs call at least somewhere in their code, so selecting
the DISPLAY_MTRRS option will always have an effect. All SoCs that don't
select RESET_VECTOR_IN_RAM have the postcar stage where it gets called.
The two AMD SoCs that select RESET_VECTOR_IN_RAM use the FSP2 driver
which contains plenty of display_mtrrs calls.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2894689ce58e7404d9d5a894f3c288bc4016ea19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>

src/cpu/intel/haswell/Kconfig

@@ -19,7 +19,6 @@ config CPU_SPECIFIC_OPTIONS
 	select CPU_INTEL_COMMON
 	select CPU_INTEL_COMMON_TIMEBASE
 	select HAVE_ASAN_IN_ROMSTAGE
-	select HAVE_DISPLAY_MTRRS
 	select CPU_INTEL_COMMON_VOLTAGE
 
 config SMM_TSEG_SIZE

src/cpu/x86/Kconfig.debug_cpu

@@ -5,12 +5,8 @@ config DEBUG_CAR
 	bool "Output verbose Cache-as-RAM debug messages"
 	depends on HAVE_DEBUG_CAR
 
-config HAVE_DISPLAY_MTRRS
-	bool
-
 config DISPLAY_MTRRS
 	bool "Display intermediate MTRR settings"
-	depends on HAVE_DISPLAY_MTRRS
 
 config DEBUG_SMM_RELOCATION
 	bool "Debug SMM relocation code"

src/soc/intel/common/Kconfig.common

@@ -1,7 +1,6 @@
 config SOC_INTEL_COMMON
 	bool
 	select AZALIA_PLUGIN_SUPPORT
-	select HAVE_DISPLAY_MTRRS
 	select ACPI_SOC_NVS
 	help
 	  common code for Intel SOCs