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cpu/x86/Kconfig.debug_cpu: drop HAVE_DISPLAY_MTRRS option 

Since all x86 CPUs in tree have MTRR support, there is no need to guard
the DISPLAY_MTRRS option with HAVE_DISPLAY_MTRRS. Also all x86 CPUs/SoCs
have a display_mtrrs call at least somewhere in their code, so selecting
the DISPLAY_MTRRS option will always have an effect. All SoCs that don't
select RESET_VECTOR_IN_RAM have the postcar stage where it gets called.
The two AMD SoCs that select RESET_VECTOR_IN_RAM use the FSP2 driver
which contains plenty of display_mtrrs calls.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2894689ce58e7404d9d5a894f3c288bc4016ea19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This commit is contained in:
Felix Held 2021-10-23 01:13:04 +02:00
parent 39789eb695
commit 761e2ae676
3 changed files with 0 additions and 6 deletions
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1
src/cpu/intel/haswell/Kconfig
View File

@ -19,7 +19,6 @@ config CPU_SPECIFIC_OPTIONS
select CPU_INTEL_COMMON select CPU_INTEL_COMMON
select CPU_INTEL_COMMON_TIMEBASE select CPU_INTEL_COMMON_TIMEBASE
select HAVE_ASAN_IN_ROMSTAGE select HAVE_ASAN_IN_ROMSTAGE
select HAVE_DISPLAY_MTRRS
select CPU_INTEL_COMMON_VOLTAGE select CPU_INTEL_COMMON_VOLTAGE
config SMM_TSEG_SIZE config SMM_TSEG_SIZE

4
src/cpu/x86/Kconfig.debug_cpu
View File

@ -5,12 +5,8 @@ config DEBUG_CAR
bool "Output verbose Cache-as-RAM debug messages" bool "Output verbose Cache-as-RAM debug messages"
depends on HAVE_DEBUG_CAR depends on HAVE_DEBUG_CAR
config HAVE_DISPLAY_MTRRS
bool
config DISPLAY_MTRRS config DISPLAY_MTRRS
bool "Display intermediate MTRR settings" bool "Display intermediate MTRR settings"
depends on HAVE_DISPLAY_MTRRS
config DEBUG_SMM_RELOCATION config DEBUG_SMM_RELOCATION
bool "Debug SMM relocation code" bool "Debug SMM relocation code"

1
src/soc/intel/common/Kconfig.common
View File

@ -1,7 +1,6 @@
config SOC_INTEL_COMMON config SOC_INTEL_COMMON
bool bool
select AZALIA_PLUGIN_SUPPORT select AZALIA_PLUGIN_SUPPORT
select HAVE_DISPLAY_MTRRS
select ACPI_SOC_NVS select ACPI_SOC_NVS
help help
common code for Intel SOCs common code for Intel SOCs