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sb/intel: Remove ENABLE_ACPI_MODE_IN_COREBOOT 

Change-Id: Ic807f4b4fc26232301f81c8076daf31fe58f217b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Kyösti Mälkki 2019-10-09 10:26:32 +03:00
parent a7fb23081c
commit 7630803b85
6 changed files with 0 additions and 48 deletions
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8
src/southbridge/intel/bd82x6x/lpc.c
View File

@ -43,8 +43,6 @@
#define NMI_OFF 0 #define NMI_OFF 0
#define ENABLE_ACPI_MODE_IN_COREBOOT 0
typedef struct southbridge_intel_bd82x6x_config config_t; typedef struct southbridge_intel_bd82x6x_config config_t;
/** /**
@ -421,15 +419,9 @@ static void enable_clock_gating(struct device *dev)
static void pch_set_acpi_mode(void) static void pch_set_acpi_mode(void)
{ {
if (!acpi_is_wakeup_s3() && CONFIG(HAVE_SMI_HANDLER)) { if (!acpi_is_wakeup_s3() && CONFIG(HAVE_SMI_HANDLER)) {
#if ENABLE_ACPI_MODE_IN_COREBOOT
printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
outb(APM_CNT_ACPI_ENABLE, APM_CNT); // Enable ACPI mode
printk(BIOS_DEBUG, "done.\n");
#else
printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n");
outb(APM_CNT_ACPI_DISABLE, APM_CNT); // Disable ACPI mode outb(APM_CNT_ACPI_DISABLE, APM_CNT); // Disable ACPI mode
printk(BIOS_DEBUG, "done.\n"); printk(BIOS_DEBUG, "done.\n");
#endif
} }
} }

8
src/southbridge/intel/i82801gx/lpc.c
View File

@ -41,8 +41,6 @@
#define NMI_OFF 0 #define NMI_OFF 0
#define ENABLE_ACPI_MODE_IN_COREBOOT 0
typedef struct southbridge_intel_i82801gx_config config_t; typedef struct southbridge_intel_i82801gx_config config_t;
/** /**
@ -338,15 +336,9 @@ static void enable_clock_gating(void)
static void i82801gx_set_acpi_mode(struct device *dev) static void i82801gx_set_acpi_mode(struct device *dev)
{ {
if (!acpi_is_wakeup_s3()) { if (!acpi_is_wakeup_s3()) {
#if ENABLE_ACPI_MODE_IN_COREBOOT
printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
outb(APM_CNT_ACPI_ENABLE, APM_CNT); // Enable ACPI mode
printk(BIOS_DEBUG, "done.\n");
#else
printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n");
outb(APM_CNT_ACPI_DISABLE, APM_CNT); // Disable ACPI mode outb(APM_CNT_ACPI_DISABLE, APM_CNT); // Disable ACPI mode
printk(BIOS_DEBUG, "done.\n"); printk(BIOS_DEBUG, "done.\n");
#endif
} else { } else {
printk(BIOS_DEBUG, "S3 wakeup, enabling ACPI via APMC\n"); printk(BIOS_DEBUG, "S3 wakeup, enabling ACPI via APMC\n");
outb(APM_CNT_ACPI_ENABLE, APM_CNT); outb(APM_CNT_ACPI_ENABLE, APM_CNT);

8
src/southbridge/intel/i82801ix/lpc.c
View File

@ -39,8 +39,6 @@
#define NMI_OFF 0 #define NMI_OFF 0
#define ENABLE_ACPI_MODE_IN_COREBOOT 0
typedef struct southbridge_intel_i82801ix_config config_t; typedef struct southbridge_intel_i82801ix_config config_t;
static void i82801ix_enable_apic(struct device *dev) static void i82801ix_enable_apic(struct device *dev)
@ -370,15 +368,9 @@ static void enable_clock_gating(void)
static void i82801ix_set_acpi_mode(struct device *dev) static void i82801ix_set_acpi_mode(struct device *dev)
{ {
if (!acpi_is_wakeup_s3()) { if (!acpi_is_wakeup_s3()) {
#if ENABLE_ACPI_MODE_IN_COREBOOT
printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
outb(APM_CNT_ACPI_ENABLE, APM_CNT); // Enable ACPI mode
printk(BIOS_DEBUG, "done.\n");
#else
printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n");
outb(APM_CNT_ACPI_DISABLE, APM_CNT); // Disable ACPI mode outb(APM_CNT_ACPI_DISABLE, APM_CNT); // Disable ACPI mode
printk(BIOS_DEBUG, "done.\n"); printk(BIOS_DEBUG, "done.\n");
#endif
} else { } else {
printk(BIOS_DEBUG, "S3 wakeup, enabling ACPI via APMC\n"); printk(BIOS_DEBUG, "S3 wakeup, enabling ACPI via APMC\n");
outb(APM_CNT_ACPI_ENABLE, APM_CNT); outb(APM_CNT_ACPI_ENABLE, APM_CNT);

8
src/southbridge/intel/i82801jx/lpc.c
View File

@ -40,8 +40,6 @@
#define NMI_OFF 0 #define NMI_OFF 0
#define ENABLE_ACPI_MODE_IN_COREBOOT 0
typedef struct southbridge_intel_i82801jx_config config_t; typedef struct southbridge_intel_i82801jx_config config_t;
static void i82801jx_enable_apic(struct device *dev) static void i82801jx_enable_apic(struct device *dev)
@ -375,15 +373,9 @@ static void enable_clock_gating(void)
static void i82801jx_set_acpi_mode(struct device *dev) static void i82801jx_set_acpi_mode(struct device *dev)
{ {
if (!acpi_is_wakeup_s3()) { if (!acpi_is_wakeup_s3()) {
#if ENABLE_ACPI_MODE_IN_COREBOOT
printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
outb(APM_CNT_ACPI_ENABLE, APM_CNT); // Enable ACPI mode
printk(BIOS_DEBUG, "done.\n");
#else
printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n");
outb(APM_CNT_ACPI_DISABLE, APM_CNT); // Disable ACPI mode outb(APM_CNT_ACPI_DISABLE, APM_CNT); // Disable ACPI mode
printk(BIOS_DEBUG, "done.\n"); printk(BIOS_DEBUG, "done.\n");
#endif
} else { } else {
printk(BIOS_DEBUG, "S3 wakeup, enabling ACPI via APMC\n"); printk(BIOS_DEBUG, "S3 wakeup, enabling ACPI via APMC\n");
outb(APM_CNT_ACPI_ENABLE, APM_CNT); outb(APM_CNT_ACPI_ENABLE, APM_CNT);

8
src/southbridge/intel/ibexpeak/lpc.c
View File

@ -43,8 +43,6 @@
#define NMI_OFF 0 #define NMI_OFF 0
#define ENABLE_ACPI_MODE_IN_COREBOOT 0
typedef struct southbridge_intel_ibexpeak_config config_t; typedef struct southbridge_intel_ibexpeak_config config_t;
/** /**
@ -431,15 +429,9 @@ static void enable_clock_gating(struct device *dev)
static void pch_set_acpi_mode(void) static void pch_set_acpi_mode(void)
{ {
if (!acpi_is_wakeup_s3() && CONFIG(HAVE_SMI_HANDLER)) { if (!acpi_is_wakeup_s3() && CONFIG(HAVE_SMI_HANDLER)) {
#if ENABLE_ACPI_MODE_IN_COREBOOT
printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
outb(APM_CNT_ACPI_ENABLE, APM_CNT); // Enable ACPI mode
printk(BIOS_DEBUG, "done.\n");
#else
printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n");
outb(APM_CNT_ACPI_DISABLE, APM_CNT); // Disable ACPI mode outb(APM_CNT_ACPI_DISABLE, APM_CNT); // Disable ACPI mode
printk(BIOS_DEBUG, "done.\n"); printk(BIOS_DEBUG, "done.\n");
#endif
} }
} }

8
src/southbridge/intel/lynxpoint/lpc.c
View File

@ -41,8 +41,6 @@
#define NMI_OFF 0 #define NMI_OFF 0
#define ENABLE_ACPI_MODE_IN_COREBOOT 0
typedef struct southbridge_intel_lynxpoint_config config_t; typedef struct southbridge_intel_lynxpoint_config config_t;
/** /**
@ -493,15 +491,9 @@ static void enable_lp_clock_gating(struct device *dev)
static void pch_set_acpi_mode(void) static void pch_set_acpi_mode(void)
{ {
if (CONFIG(HAVE_SMI_HANDLER) && !acpi_is_wakeup_s3()) { if (CONFIG(HAVE_SMI_HANDLER) && !acpi_is_wakeup_s3()) {
#if ENABLE_ACPI_MODE_IN_COREBOOT
printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
outb(APM_CNT_ACPI_ENABLE, APM_CNT);
printk(BIOS_DEBUG, "done.\n");
#else
printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n");
outb(APM_CNT_ACPI_DISABLE, APM_CNT); outb(APM_CNT_ACPI_DISABLE, APM_CNT);
printk(BIOS_DEBUG, "done.\n"); printk(BIOS_DEBUG, "done.\n");
#endif
} }
} }