armv7: Add emulation/qemu-armv7 board.
To simplify testing ARM implementation, we need a QEMU configuration for ARM. The qemu-armv7 provides serial output, CBFS simulation, and full boot path (bootblock, romstage, ramstage) to verify the boot loader functionality. To run with QEMU: export QEMU_AUDIO_DRV=none qemu-system-arm -M vexpress-a9 -m 1024M -nographic -kernel build/coreboot.rom Verified to boot until ramstage loaded successfully by QEMU v1.0.50. Change-Id: I1f23ffaf408199811a0756236821c7e0f2a85004 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2354 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
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@ -3,6 +3,7 @@
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# (See also src/Kconfig)
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if ARCH_ARMV7
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source src/cpu/armltd/Kconfig
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source src/cpu/samsung/Kconfig
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endif # ARCH_ARM
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@ -2,6 +2,7 @@
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## Subdirectories
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################################################################################
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subdirs-y += amd
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subdirs-y += armltd
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subdirs-y += intel
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subdirs-y += samsung
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subdirs-y += via
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@ -0,0 +1,8 @@
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config CPU_ARMLTD_CORTEX_A9
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depends on ARCH_ARMV7
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bool
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default n
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if CPU_ARMLTD_CORTEX_A9
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source src/cpu/armltd/cortex-a9/Kconfig
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endif
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@ -0,0 +1 @@
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subdirs-$(CONFIG_CPU_ARMLTD_CORTEX_A9) += cortex-a9
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@ -0,0 +1,5 @@
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config BOOTBLOCK_CPU_INIT
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string
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default "cpu/armltd/cortex-a9/bootblock.c"
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help
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CPU/SoC-specific bootblock code.
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@ -0,0 +1,2 @@
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ramstage-y += cache.c
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romstage-y += cache.c
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@ -0,0 +1,17 @@
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/*
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* Copyright (C) 2013 Google, Inc.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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void bootblock_cpu_init(void);
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void bootblock_cpu_init(void)
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{
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}
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@ -0,0 +1,44 @@
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/*
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* Copyright (C) 2013 Google, Inc.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <common.h>
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#include <system.h>
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#include <armv7.h>
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/*
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* Sets L2 cache related parameters before enabling data cache
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*/
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void v7_outer_cache_enable(void)
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{
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}
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/* stubs so we don't need weak symbols in cache_v7.c */
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void v7_outer_cache_disable(void)
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{
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}
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void v7_outer_cache_flush_all(void)
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{
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}
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void v7_outer_cache_inval_all(void)
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{
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}
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void v7_outer_cache_flush_range(u32 start, u32 end)
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{
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}
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void v7_outer_cache_inval_range(u32 start, u32 end)
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{
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}
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@ -6,9 +6,13 @@ choice
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config BOARD_EMULATION_QEMU_X86
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bool "QEMU x86"
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config BOARD_EMULATION_QEMU_ARMV7
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bool "QEMU armv7 (vexpress-a9)"
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endchoice
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source "src/mainboard/emulation/qemu-x86/Kconfig"
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source "src/mainboard/emulation/qemu-armv7/Kconfig"
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config MAINBOARD_VENDOR
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string
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2013 Google Inc.
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##
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## This software is licensed under the terms of the GNU General Public
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## License version 2, as published by the Free Software Foundation, and
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## may be copied, distributed, and modified under those terms.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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# Emulation for ARM Ltd Versatile Express Cortex-A9
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# http://www.arm.com/products/tools/development-boards/versatile-express
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# To execute, do:
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# export QEMU_AUDIO_DRV=none
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# qemu-system-arm -M vexpress-a9 -m 1024M -nographic -kernel build/coreboot.rom
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if BOARD_EMULATION_QEMU_ARMV7
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select ARCH_ARMV7
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select CPU_ARMLTD_CORTEX_A9
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select DEFAULT_EARLY_CONSOLE
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select HAVE_UART_SPECIAL
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select BOARD_ROMSIZE_KB_4096
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config MAINBOARD_DIR
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string
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default emulation/qemu-armv7
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config MAINBOARD_PART_NUMBER
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string
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default "QEMU ARMV7"
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config MAX_CPUS
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int
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default 2
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config MAINBOARD_VENDOR
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string
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default "ARM Ltd."
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config BOOTBLOCK_MAINBOARD_INIT
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string
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default "mainboard/emulation/qemu-armv7/bootblock.c"
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config DRAM_SIZE_MB
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int
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default 1024
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# Memory map for qemu vexpress-a9:
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#
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# 0x0000_0000: jump instruction (by qemu)
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# 0x0001_0000: bootblock (entry of kernel / firmware)
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# 0x0002_0000: romstage, assume up to 128KB in size.
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# 0x0007_ff00: stack pointer
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# 0x0010_0000: CBFS header
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# 0x0011_0000: CBFS data
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# 0x0100_0000: reserved for ramstage
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# 0x1000_0000: I/O map address
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config BOOTBLOCK_BASE
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hex
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default 0x00010000
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config ID_SECTION_BASE
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hex
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default 0x0001f000
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config ROMSTAGE_BASE
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hex
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default 0x00020000
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config ROMSTAGE_SIZE
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hex
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default 0x20000
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config CBFS_HEADER_ROM_OFFSET
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hex
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default 0x0100000
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config CBFS_ROM_OFFSET
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hex
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default 0x0110000
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config IRAM_STACK
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hex
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default 0x0007ff00
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config XIP_ROM_SIZE
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hex
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default ROMSTAGE_SIZE
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config SYS_SDRAM_BASE
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hex "SDRAM base address"
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default 0x01000000
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config SYS_TEXT_BASE
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hex "Executable code section"
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default 0x04e00000
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config RAMBASE
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hex
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default SYS_SDRAM_BASE
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# according to stefan, this is RAMBASE + 1M.
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config RAMTOP
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hex
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default 0x01100000
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endif # BOARD_EMULATION_QEMU_ARMV7
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@ -0,0 +1,30 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2013 Google Inc.
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##
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## This software is licensed under the terms of the GNU General Public
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## License version 2, as published by the Free Software Foundation, and
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## may be copied, distributed, and modified under those terms.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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romstage-y += romstage.c
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ramstage-y += ramstage.c
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bootblock-y += media.c
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romstage-y += media.c
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ramstage-y += media.c
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bootblock-y += timer.c
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romstage-y += timer.c
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ramstage-y += timer.c
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bootblock-$(CONFIG_EARLY_CONSOLE) += uart.c
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romstage-$(CONFIG_EARLY_CONSOLE) += uart.c
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ramstage-y += uart.c
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SRC_ROOT = $(src)/mainboard/emulation/qemu-armv7a
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google, Inc.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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void bootblock_mainboard_init(void);
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void bootblock_mainboard_init(void)
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{
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console_init();
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printk(BIOS_INFO, "\n\n\n%s: ARMv7 Emulation Started.\n", __func__);
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}
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2013 Google, Inc.
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##
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## This software is licensed under the terms of the GNU General Public
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## License version 2, as published by the Free Software Foundation, and
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## may be copied, distributed, and modified under those terms.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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# TODO fill with Versatile Express board data in QEMU.
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chip cpu/armltd/cortex-a9
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chip drivers/generic/generic # I2C0 controller
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device i2c 6 on end # Fake component for testing
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end
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end
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google, Inc.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <device/device.h>
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static void enable_dev(device_t dev)
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{
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printk(BIOS_INFO, "Enable qemu/armv7 device...\n");
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}
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struct chip_operations mainboard_ops = {
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.enable_dev = enable_dev,
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};
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google, Inc.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <cbfs.h>
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#include <string.h>
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#include <console/console.h>
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/* Simple memory-mapped ROM emulation. */
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static int emu_rom_open(struct cbfs_media *media) {
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return 0;
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}
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static void *emu_rom_map(struct cbfs_media *media, size_t offset, size_t count) {
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return (void*)(offset + CONFIG_BOOTBLOCK_BASE);
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}
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static void *emu_rom_unmap(struct cbfs_media *media, const void *address) {
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return NULL;
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}
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static size_t emu_rom_read(struct cbfs_media *media, void *dest, size_t offset,
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size_t count) {
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void *ptr = emu_rom_map(media, offset, count);
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memcpy(dest, ptr, count);
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emu_rom_unmap(media, ptr);
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return count;
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}
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static int emu_rom_close(struct cbfs_media *media) {
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return 0;
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}
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int init_emu_rom_cbfs_media(struct cbfs_media *media);
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int init_emu_rom_cbfs_media(struct cbfs_media *media) {
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media->open = emu_rom_open;
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media->close = emu_rom_close;
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media->map = emu_rom_map;
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media->unmap = emu_rom_unmap;
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media->read = emu_rom_read;
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return 0;
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}
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int init_default_cbfs_media(struct cbfs_media *media) {
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return init_emu_rom_cbfs_media(media);
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}
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google, Inc.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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void hardwaremain(int boot_complete);
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void main(void)
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{
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console_init();
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printk(BIOS_INFO, "hello from ramstage\n");
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hardwaremain(0);
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}
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google, Inc.
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*
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* This software is licensed under the terms of the GNU General Public
|
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* License version 2, as published by the Free Software Foundation, and
|
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
|
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <cbfs.h>
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#include <common.h>
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#include <console/console.h>
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#include <arch/stages.h>
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void main(void)
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{
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void *entry;
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console_init();
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printk(BIOS_INFO, "hello from romstage\n");
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entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram");
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printk(BIOS_INFO, "entry is 0x%p, leaving romstage.\n", entry);
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stage_exit(entry);
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}
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google, Inc.
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*
|
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* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
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* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
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*/
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void udelay(unsigned int n);
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void udelay(unsigned int n) {
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/* TODO provide delay here. */
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}
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int init_timer(void);
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int init_timer(void) {
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return 0;
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}
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/*
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* This file is part of the coreboot project.
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*
|
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* Copyright (C) 2013 Google, Inc.
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
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#include <console/console.h>
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#include <uart.h>
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#define VEXPRESS_UART0_IO_ADDRESS (0x10009000)
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static void pl011_init_dev(void) {
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}
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|
||||
static void pl011_uart_tx_byte(unsigned char data) {
|
||||
static volatile unsigned int *uart0_address =
|
||||
(unsigned int *)VEXPRESS_UART0_IO_ADDRESS;
|
||||
|
||||
*uart0_address = (unsigned int)data;
|
||||
}
|
||||
|
||||
static void pl011_uart_tx_flush(void) {
|
||||
}
|
||||
|
||||
#if !defined(__PRE_RAM__)
|
||||
|
||||
static const struct console_driver pl011_uart_console __console = {
|
||||
.init = pl011_init_dev,
|
||||
.tx_byte = pl011_uart_tx_byte,
|
||||
.tx_flush = pl011_uart_tx_flush,
|
||||
};
|
||||
|
||||
#else
|
||||
void uart_init(void)
|
||||
{
|
||||
pl011_init_dev();
|
||||
}
|
||||
|
||||
void uart_tx_byte(unsigned char data)
|
||||
{
|
||||
pl011_uart_tx_byte(data);
|
||||
}
|
||||
|
||||
void uart_tx_flush(void) {
|
||||
pl011_uart_tx_flush();
|
||||
}
|
||||
#endif
|
Loading…
Reference in New Issue