soc/amd/stoneyridge: Add XHCI PM register access functions
Add functions to access the XHCI PM MMIO registers. Change-Id: I81b4c0a448eb17c5ee0562a2c3548a074d533a98 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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@ -31,6 +31,7 @@
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#define AMD_SB_ACPI_MMIO_ADDR 0xfed80000
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#define APU_SMI_BASE 0xfed80200
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#define PM_MMIO_BASE 0xfed80300
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#define XHCI_ACPI_PM_MMIO_BASE 0xfed81c00
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#define APU_UART0_BASE 0xfedc6000
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#define APU_UART1_BASE 0xfedc8000
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@ -312,6 +312,12 @@ void smi_write16(uint8_t offset, uint16_t value);
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void smi_write32(uint8_t offset, uint32_t value);
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uint16_t pm_acpi_pm_cnt_blk(void);
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uint16_t pm_acpi_pm_evt_blk(void);
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void xhci_pm_write8(uint8_t reg, uint8_t value);
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uint8_t xhci_pm_read8(uint8_t reg);
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void xhci_pm_write16(uint8_t reg, uint16_t value);
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uint16_t xhci_pm_read16(uint8_t reg);
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void xhci_pm_write32(uint8_t reg, uint32_t value);
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uint32_t xhci_pm_read32(uint8_t reg);
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int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
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int s3_save_nvram_early(u32 dword, int size, int nvram_pos);
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void bootblock_fch_early_init(void);
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@ -84,3 +84,33 @@ uint16_t pm_acpi_pm_evt_blk(void)
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{
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return pm_read16(PM_EVT_BLK);
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}
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void xhci_pm_write8(uint8_t reg, uint8_t value)
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{
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write8((void *)(XHCI_ACPI_PM_MMIO_BASE + reg), value);
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}
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uint8_t xhci_pm_read8(uint8_t reg)
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{
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return read8((void *)(XHCI_ACPI_PM_MMIO_BASE + reg));
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}
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void xhci_pm_write16(uint8_t reg, uint16_t value)
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{
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write16((void *)(XHCI_ACPI_PM_MMIO_BASE + reg), value);
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}
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uint16_t xhci_pm_read16(uint8_t reg)
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{
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return read16((void *)(XHCI_ACPI_PM_MMIO_BASE + reg));
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}
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void xhci_pm_write32(uint8_t reg, uint32_t value)
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{
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write32((void *)(XHCI_ACPI_PM_MMIO_BASE + reg), value);
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}
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uint32_t xhci_pm_read32(uint8_t reg)
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{
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return read32((void *)(XHCI_ACPI_PM_MMIO_BASE + reg));
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}
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