soc/qualcomm: Add generic support skeleton for ipq806x
Skeleton for soc ipq806x Old-Change-Id: I92a8d592d762f59665e15d1a7fc6cc73dc74c296 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/190723 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit e71d45733d86e77717fd2f592ef06113246db911) soc/ipq806x: Disable LPAE mode. LPAE (large physical address extension) is not available on this SOC core, do not enable it. Old-Change-Id: I9e9ad1aeaf613f04987c0c306a574085042d0e7b Signed-off-by: Deepa Dinamani <deepad@codeaurora.com> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/198023 Reviewed-by: deepa dinamani <deepad@quicinc.com> (cherry picked from commit e6e12c39efd54e4fcbd444134bf30e211948a71b) Squashed 2 commits for the Qualcomm ipq806x SOC. Change-Id: I14521d3b2844ddd68112882de81453ce8d19fc16 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6963 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
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source src/soc/intel/Kconfig
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source src/soc/intel/Kconfig
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source src/soc/nvidia/Kconfig
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source src/soc/nvidia/Kconfig
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source src/soc/qualcomm/Kconfig
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source src/soc/samsung/Kconfig
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source src/soc/samsung/Kconfig
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################################################################################
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################################################################################
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subdirs-y += intel
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subdirs-y += intel
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subdirs-y += nvidia
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subdirs-y += nvidia
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subdirs-y += qualcomm
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subdirs-y += samsung
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subdirs-y += samsung
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source src/soc/qualcomm/ipq806x/Kconfig
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subdirs-$(CONFIG_SOC_QC_IPQ806X) += ipq806x
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config SOC_QC_IPQ806X
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select ARCH_BOOTBLOCK_ARMV4
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select ARCH_ROMSTAGE_ARMV7
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select ARCH_RAMSTAGE_ARMV7
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bool
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default n
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if SOC_QC_IPQ806X
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config BOOTBLOCK_ROM_OFFSET
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hex
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default 0x0
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config CBFS_HEADER_ROM_OFFSET
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hex "offset of master CBFS header in ROM"
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default 0x18000
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config CBFS_ROM_OFFSET
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hex "offset of CBFS data in ROM"
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default 0x18080
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endif
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bootblock-y += cbfs.c
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bootblock-y += timer.c
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romstage-y += cbfs.c
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romstage-y += timer.c
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ramstage-y += cbfs.c
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ramstage-y += timer.c
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <cbfs.h> /* This driver serves as a CBFS media source. */
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int init_default_cbfs_media(struct cbfs_media *media)
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{
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return 0;
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}
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <timer.h>
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#include <delay.h>
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#include <thread.h>
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void init_timer(void)
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{
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}
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