rockchip: gru: Add USB DRD DWC3 controller support
This patch adds code to initialize the two DWC3 USB host controllers, and uses them to initialize USB3.0 on the gru rk3399 board. BRANCH=none BUG=chrome-os-partner:52684 TEST=boot from USB3.0 on gru/kevin rk3399 platform Change-Id: If6a6e56f3a7c7ce8e8b098634cfc2f250a91810d Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 0306a9e Original-Change-Id: I796fa1133510876f75873d134ea752e1b52e40a8 Original-Signed-off-by: Liangfeng Wu <wulf@rock-chips.com> Original-Signed-off-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/347524 Original-Commit-Ready: Brian Norris <briannorris@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/15112 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Liangfeng Wu
Martin Roth
parent
8c7e416309
commit
76655cb82c
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@ -24,6 +24,7 @@
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#include <soc/emmc.h>
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#include <soc/grf.h>
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#include <soc/i2c.h>
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#include <soc/usb.h>
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#include "board.h"
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@ -118,12 +119,19 @@ static void configure_display(void)
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gpio_output(GPIO(4, D, 3), 1); /* CPU3_EDP_VDDEN for P3.3V_DISP */
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}
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static void setup_usb(void)
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{
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setup_usb_drd0_dwc3();
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setup_usb_drd1_dwc3();
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}
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static void mainboard_init(device_t dev)
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{
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configure_sdmmc();
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configure_emmc();
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configure_codec();
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configure_display();
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setup_usb();
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}
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static void enable_backlight_booster(void)
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@ -47,6 +47,7 @@ romstage-y += ../common/pwm.c
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romstage-y += timer.c
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romstage-y += romstage.c
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romstage-y += tsadc.c
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romstage-y += usb.c
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romstage-y += gpio.c
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romstage-y += ../common/gpio.c
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@ -67,6 +68,7 @@ ramstage-y += saradc.c
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ramstage-y += soc.c
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ramstage-y += timer.c
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ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += ../common/vop.c
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ramstage-y += usb.c
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BL31_MAKEARGS += PLAT=rk3399
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################################################################################
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@ -70,6 +70,9 @@
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#define DDRC1_BASE_ADDR 0xffa88000
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#define SERVER_MSCH1_BASE_ADDR 0xffa8c000
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#define USB_DRD0_DWC3_BASE 0xfe80c100
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#define USB_DRD1_DWC3_BASE 0xfe90c100
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#define IC_BASES { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, \
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I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE, I2C8_BASE }
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@ -0,0 +1,121 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 Rockchip, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __SOC_ROCKCHIP_RK3399_USB_H_
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#define __SOC_ROCKCHIP_RK3399_USB_H_
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#include <soc/addressmap.h>
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/* Global constants */
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#define DWC3_GSNPSID_MASK 0xffff0000
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#define DWC3_GSNPSID_SHIFT 16
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#define DWC3_GSNPSREV_MASK 0xffff
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/* Global Configuration Register */
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#define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19)
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#define DWC3_GCTL_U2RSTECN (1 << 16)
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#define DWC3_GCTL_RAMCLKSEL(x) \
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(((x) & DWC3_GCTL_CLK_MASK) << 6)
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#define DWC3_GCTL_CLK_BUS (0)
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#define DWC3_GCTL_CLK_PIPE (1)
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#define DWC3_GCTL_CLK_PIPEHALF (2)
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#define DWC3_GCTL_CLK_MASK (3)
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#define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12)
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#define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12)
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#define DWC3_GCTL_PRTCAP_HOST 1
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#define DWC3_GCTL_PRTCAP_DEVICE 2
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#define DWC3_GCTL_PRTCAP_OTG 3
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#define DWC3_GCTL_CORESOFTRESET (1 << 11)
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#define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)
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#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
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#define DWC3_GCTL_DISSCRAMBLE (1 << 3)
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#define DWC3_GCTL_DSBLCLKGTNG (1 << 0)
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/* Global HWPARAMS1 Register */
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#define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24)
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#define DWC3_GHWPARAMS1_EN_PWROPT_NO 0
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#define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1
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/* Global USB2 PHY Configuration Register */
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#define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31)
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#define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS (1 << 30)
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#define DWC3_GUSB2PHYCFG_USBTRDTIM(n) ((n) << 10)
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#define DWC3_GUSB2PHYCFG_USB2TRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf)
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#define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6)
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#define DWC3_GUSB2PHYCFG_PHYIF(n) ((n) << 3)
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#define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1)
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#define USBTRDTIM_UTMI_8_BIT 9
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#define USBTRDTIM_UTMI_16_BIT 5
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/* Global USB3 PIPE Control Register */
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#define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31)
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#define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17)
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struct rockchip_usb_drd_dwc3 {
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uint32_t sbuscfg0;
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uint32_t sbuscfg1;
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uint32_t txthrcfg;
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uint32_t rxthrcfg;
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uint32_t ctl;
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uint32_t evten;
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uint32_t sts;
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uint8_t reserved0[4];
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uint32_t snpsid;
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uint32_t gpio;
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uint32_t uid;
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uint32_t uctl;
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uint64_t buserraddr;
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uint64_t prtbimap;
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uint32_t hwparams0;
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uint32_t hwparams1;
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uint32_t hwparams2;
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uint32_t hwparams3;
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uint32_t hwparams4;
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uint32_t hwparams5;
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uint32_t hwparams6;
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uint32_t hwparams7;
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uint32_t dbgfifospace;
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uint32_t dbgltssm;
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uint32_t dbglnmcc;
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uint32_t dbgbmu;
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uint32_t dbglspmux;
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uint32_t dbglsp;
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uint32_t dbgepinfo0;
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uint32_t dbgepinfo1;
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uint64_t prtbimap_hs;
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uint64_t prtbimap_fs;
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uint8_t reserved2[112];
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uint32_t usb2phycfg;
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uint8_t reserved3[60];
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uint32_t usb2i2cctl;
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uint8_t reserved4[60];
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uint32_t usb2phyacc;
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uint8_t reserved5[60];
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uint32_t usb3pipectl;
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uint8_t reserved6[60];
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};
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static struct rockchip_usb_drd_dwc3 * const rockchip_usb_drd0_dwc3 =
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(void *)USB_DRD0_DWC3_BASE;
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static struct rockchip_usb_drd_dwc3 * const rockchip_usb_drd1_dwc3 =
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(void *)USB_DRD1_DWC3_BASE;
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/* Call reset _ before setup_ */
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void reset_usb_drd0_dwc3(void);
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void reset_usb_drd1_dwc3(void);
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void setup_usb_drd0_dwc3(void);
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void setup_usb_drd1_dwc3(void);
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#endif /* __SOC_ROCKCHIP_RK3399_USB_H_ */
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@ -31,6 +31,7 @@
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#include <soc/tsadc.h>
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#include <soc/sdram.h>
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#include <symbols.h>
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#include <soc/usb.h>
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static const uint64_t dram_size =
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(uint64_t)min((uint64_t)CONFIG_DRAM_SIZE_MB * MiB, MAX_DRAM_ADDRESS);
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@ -72,6 +73,16 @@ static void init_dvs_outputs(void)
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pwm_init(i, 3333, 1904);
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}
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static void prepare_usb(void)
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{
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/*
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* Do dwc3 core soft reset and phy reset. Kick these resets
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* off early so they get at least 100ms to settle.
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*/
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reset_usb_drd0_dwc3();
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reset_usb_drd1_dwc3();
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}
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void main(void)
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{
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console_init();
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@ -81,6 +92,8 @@ void main(void)
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/* Init DVS to conservative values. */
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init_dvs_outputs();
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prepare_usb();
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sdram_init(get_sdram_config());
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mmu_config_range((void *)0, (uintptr_t)dram_size, CACHED_MEM);
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@ -0,0 +1,107 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 Rockchip, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <console/console.h>
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#include <delay.h>
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#include <soc/usb.h>
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static void reset_dwc3(struct rockchip_usb_drd_dwc3 *dwc3_reg)
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{
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/* Before Resetting PHY, put Core in Reset */
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setbits_le32(&dwc3_reg->ctl, DWC3_GCTL_CORESOFTRESET);
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/* Assert USB3 PHY reset */
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setbits_le32(&dwc3_reg->usb3pipectl, DWC3_GUSB3PIPECTL_PHYSOFTRST);
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/* Assert USB2 PHY reset */
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setbits_le32(&dwc3_reg->usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
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}
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static void setup_dwc3(struct rockchip_usb_drd_dwc3 *dwc3_reg)
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{
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u32 reg;
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u32 revision;
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u32 dwc3_hwparams1;
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/* Clear USB3 PHY reset */
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clrbits_le32(&dwc3_reg->usb3pipectl, DWC3_GUSB3PIPECTL_PHYSOFTRST);
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/* Clear USB2 PHY reset */
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clrbits_le32(&dwc3_reg->usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
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/* After PHYs are stable we can take Core out of reset state */
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clrbits_le32(&dwc3_reg->ctl, DWC3_GCTL_CORESOFTRESET);
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revision = read32(&dwc3_reg->snpsid);
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/* This should read as U3 followed by revision number */
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if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) {
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printk(BIOS_ERR, "ERROR: not a DesignWare USB3 DRD Core\n");
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return;
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}
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dwc3_hwparams1 = read32(&dwc3_reg->hwparams1);
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reg = read32(&dwc3_reg->ctl);
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reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
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reg &= ~DWC3_GCTL_DISSCRAMBLE;
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if (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1) ==
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DWC3_GHWPARAMS1_EN_PWROPT_CLK)
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reg &= ~DWC3_GCTL_DSBLCLKGTNG;
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else
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printk(BIOS_DEBUG, "No power optimization available\n");
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write32(&dwc3_reg->ctl, reg);
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/* We are hard-coding DWC3 core to Host Mode */
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clrsetbits_le32(&dwc3_reg->ctl,
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DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG),
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DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_HOST));
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/*
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* Configure USB phy interface of DWC3 core.
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* For Rockchip rk3399 SOC DWC3 core:
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* 1. Clear U2_FREECLK_EXITS.
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* 2. Select UTMI+ PHY with 16-bit interface.
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* 3. Set USBTRDTIM to the corresponding value
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* according to the UTMI+ PHY interface.
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*/
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reg = read32(&dwc3_reg->usb2phycfg);
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reg &= ~(DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS |
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DWC3_GUSB2PHYCFG_USB2TRDTIM_MASK |
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DWC3_GUSB2PHYCFG_PHYIF_MASK);
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reg |= DWC3_GUSB2PHYCFG_PHYIF(1) |
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DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
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write32(&dwc3_reg->usb2phycfg, reg);
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}
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void reset_usb_drd0_dwc3(void)
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{
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printk(BIOS_DEBUG, "Starting DWC3 reset for USB DRD0\n");
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reset_dwc3(rockchip_usb_drd0_dwc3);
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}
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void reset_usb_drd1_dwc3(void)
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{
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printk(BIOS_DEBUG, "Starting DWC3 reset for USB DRD1\n");
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reset_dwc3(rockchip_usb_drd1_dwc3);
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}
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void setup_usb_drd0_dwc3(void)
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{
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setup_dwc3(rockchip_usb_drd0_dwc3);
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printk(BIOS_DEBUG, "DWC3 setup for USB DRD0 finished\n");
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}
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void setup_usb_drd1_dwc3(void)
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{
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setup_dwc3(rockchip_usb_drd1_dwc3);
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printk(BIOS_DEBUG, "DWC3 setup for USB DRD1 finished\n");
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}
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